Let m be the miss rate of the cache, and h=1−m be the hit rate.
The average read latency Tavg is given by:
Tavg=(1−m)×Tcache+m×Tdisk Given:
Tcache=1 ms
Tdisk=10 ms
Desired Tavg<6 ms
Substitute the values into the inequality:
(1−m)×1+m×10<6 1−m+10m<6 9m<5⟹m<95≈55.56% From the given miss rate graph:
For cache size =10 MB, miss rate =80%
For cache size =20 MB, miss rate =60%
For cache size =30 MB, miss rate =40%
For cache size =40 MB, miss rate =35%
For Tavg<6 ms, we require m<55.56%.
At 20 MB, m=60%>55.56% (Tavg=0.4(1)+0.6(10)=6.4 ms).
At 30 MB, m=40%<55.56% (Tavg=0.6(1)+0.4(10)=4.6 ms).
Thus, the smallest available cache size meeting the requirement is 30 MB.