What are common examiner traps in Computer Organization and Architecture?

Confusing word addressability with byte addressability (e.g., assuming 1 address = 1 byte when word size is given as 2 or 4 bytes). Misinterpreting local miss rate vs. global miss rate in multi-level caches (e.g., using misses per 1000 instructions as local miss rate without dividing by L1 misses). Adding L1 access time twice when formula uses hierarchical format vs miss penalty format. Assuming Write-Through caches have dirty bits, or forgetting that dirty blocks in Write-Back are only written back upon eviction (not on the initial write hit). Forgetting that compulsory misses occur strictly on the first global reference to a distinct block, not on subsequent conflicts in a looped trace. Forgetting that increasing associativity k 2k keeps Tag + Index constant, thus increasing tag bits by 1 bit and reducing index bits by 1 bit. Multiplying tag directory entry size by number of sets instead of total number of cache lines (blocks). Confusing number of sets v with associativity k in modulo mapping (j v vs j k).

Computer Organization and Architecture

6 topics · 109 Qs · 7.1 marks/paper · since 2011

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Memory hierarchy and cache mapping is one of the highest-yield, most quantitative topics in GATE Computer Science, regularly tested through 2-mark NAT and MSQ questions. Instructio… Guide

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Subject guide

What does GATE test in Computer Organization and Architecture?

Memory hierarchy and cache mapping is one of the highest-yield, most quantitative topics in GATE Computer Science, regularly tested through 2-mark NAT and MSQ questions. Instruction pipelining and pipeline hazards are tested extensively with a heavy numerical skew (primarily 2-mark NATs). Instruction set and addressing modes in GATE CS is consistently tested through instruction word encoding, expanding opcode schemes, addressing mode semantics, and ISA architectural principles.

Core concepts

Direct, fully-associative, and k-way set-associative cache mapping
Physical vs. Virtual indexing and Tagging (Page coloring for aliasing)
Hierarchical vs. Simultaneous memory access models
Average Memory Access Time (AMAT) and stall cycles per instruction
Separate Instruction (I-Cache) and Data (D-Cache) hierarchies
Write-Through with No-Write Allocate vs. Write-Back with Write Allocate
Dirty (Modified) bit and Valid bit mechanics during hit/miss/eviction
Block replacement algorithms (LRU, FIFO) and reference string simulation
Compulsory (cold), Capacity, and Conflict misses
Memory interleaving, bank cycle time, and bus bottleneck analysis
Magnetic disk drive geometry and capacity calculations
Address decomposition: Tag, Set Index, and Word/Byte Offset fields

High-yield formulas

Cache Line Count

\text{Number of Lines } (N) = \frac{\text{Cache Capacity}}{\text{Block Size}}

Determining total cache lines before calculating index bits or set counts.

Number of Sets in $k$-Way Set Associative Cache

\text{Number of Sets } (S) = \frac{N}{k} = \frac{\text{Cache Capacity}}{k \times \text{Block Size}}

Determining set index bits in set-associative cache mappings.

Address Field Partitioning

\text{Address Bits} = \text{Tag Bits} + \log_2(S) + \log_2(\text{Block Size in Bytes})

Calculating tag size or verifying total physical address width.

Tag Invariance with Block Size

\text{Set Index Bits} + \text{Block Offset Bits} = \log_2\left(\frac{\text{Cache Capacity}}{k}\right)

Solving for tag width when block size is unknown or variable.

Total Tag Memory Overhead

\text{Total Tag Storage} = N \times (\text{Tag Bits} + \text{Valid Bit} + \text{Dirty Bit})

Calculating the total hardware memory needed to store cache tags and status bits.

Hierarchical Two-Level AMAT

\text{AMAT} = T_{L1} + (1 - H_{L1}) \times \left( T_{L2} + (1 - H_{L2}) \times T_{MM} \right)

Calculating average access time when miss penalties are resolved hierarchically level-by-level.

CPI with Split Memory Stalls

\text{CPI}_{\text{actual}} = \text{CPI}_{\text{ideal}} + (1 \times m_I \times P_I) + (f_{\text{data}} \times m_D \times P_D)

Calculating processor stall overhead for separate instruction and data caches.

Hard Disk Capacity

\text{Capacity} = \text{Cylinders} \times \text{Surfaces} \times \frac{\text{Sectors}}{\text{Track}} \times \frac{\text{Bytes}}{\text{Sector}}

Solving for disk geometry parameters from total formatted capacity.

Examiner traps in Computer Organization and Architecture

Confusing word addressability with byte addressability (e.g., assuming 1 address = 1 byte when word size is given as 2 or 4 bytes).
Misinterpreting local miss rate vs. global miss rate in multi-level caches (e.g., using misses per 1000 instructions as local miss rate without dividing by L1 misses).
Adding L1 access time twice when formula uses hierarchical format vs miss penalty format.
Assuming Write-Through caches have dirty bits, or forgetting that dirty blocks in Write-Back are only written back upon eviction (not on the initial write hit).
Forgetting that compulsory misses occur strictly on the first global reference to a distinct block, not on subsequent conflicts in a looped trace.
Forgetting that increasing associativity k 2k keeps Tag + Index constant, thus increasing tag bits by 1 bit and reducing index bits by 1 bit.
Multiplying tag directory entry size by number of sets instead of total number of cache lines (blocks).
Confusing number of sets v with associativity k in modulo mapping (j v vs j k).

How questions show up

Cache Address Field Decomposition and Tag Sizing
common · NAT · 2 marks · 2026, 2025, 2023, 2021
Given physical address size, cache capacity, block size, and associativity (or variations where one parameter is unknown or parameterized by variables), calculate the width of Tag, Set Index, or Offset bits, or total tag memory required.
Multi-Level Cache AMAT and CPI Stall Analysis
common · NAT · 2 marks · 2025, 2024, 2022, 2017
Given L1/L2 access times, local/global hit rates, and main memory miss penalties (often separated into I-cache and D-cache or read/write distributions), calculate AMAT, effective CPI, or minimum required hit rate after optimization.
Address Trace Simulation and Cache Conflict/Hit Analysis
common · MSQ · 2 marks · 2026, 2022, 2017, 2014
Given a sequence of hex addresses or block numbers accessed in a loop over a specific cache organization, trace compulsory vs conflict misses, hit/miss outcomes for specific references, and final cache contents.
Write Policy Conceptual Analysis
occasional · MSQ · 2 marks · 2024, 2022
Evaluate architectural assertions regarding Write-Back vs. Write-Through policies, dirty bit necessity, eviction penalties on read/write misses, and memory bus traffic.
Memory Interleaving and Secondary Storage Geometry
occasional · NAT · 2 marks · 2024, 2016, 2014
Calculate throughput/initiation rates in multi-module interleaved memory systems or solve for disk geometry parameters (cylinders, surfaces, sectors) from capacity constraints.
Cache Address Breakdown and Tag Directory Size Calculation
common · MCQ · 2 marks · 2012
Given physical address size, cache capacity, associativity, and block size, calculate the number of tag bits and the total size in bits/Kbits of the tag directory (including status bits like valid, modified/dirty, replacement bits).