GateAI
Code Generation

GATE CSE 2013 · Q49

MCQ2 marksMedium

Time

Common Data for Questions 48 and 49

The following code segment is executed on a processor which allows only register operands in its instructions. Each instruction can have atmost two source operands and one destination operand. Assume that all variables are dead after this code segment.c = a + b; d = c * a; e = c + a; x = c * c; if (x > a) { y = a * a; } else { d = d * d; e = e * e; }What is the minimum number of registers needed in the instruction set architecture of the processor to compile this code segment without any spill to memory? Do not apply any optimization other than optimizing register allocation.

Select one answerSingle correct

Pick an option to check

Solution

Step-by-step verified solution

Official answer: B) 4

Code Generation

Without code motion or other optimizations, we determine the maximum number of simultaneously live variables at any point during execution:

  1. Initially, variables aa and bb are live (2 variables).

  2. After c = a + b: bb is dead, so live variables are {a,c}\{a, c\} (2 variables).

  3. After d = c * a: live variables are {a,c,d}\{a, c, d\} (3 variables).

  4. After e = c + a: live variables are {a,c,d,e}\{a, c, d, e\} (4 variables).

  5. After x = c * c: cc is now dead, so live variables are {a,d,e,x}\{a, d, e, x\} (4 variables).

  6. At if (x > a): xx is consumed, leaving {a,d,e}\{a, d, e\} live (3 variables).

  7. In the if block, y=a∗ay = a * a is computed.

  8. In the else block, dd and ee are used and updated.

The maximum number of simultaneously live variables at any point is 4 (specifically, after computing ee and xx). Hence, at least 4 registers are needed to compile the code without any memory spills.

Try the question first, then check your work.

Think the official key or this write-up is wrong?

Report error or challenge

Examiner trap

The misconception this question tests

This Code Generation previous year question is Q49 of the GATE CSE 2013 paper. Find more GATE CSE PYQs on Code Generation in Compiler Design, or browse all GATE CSE PYQs.

Free diagnostic

Where do you stand for GATE?

Take the 20-minute diagnostic: the 3 topics that cost you the most marks, and a rank range. Or sit 1 related Code Generation PYQs now with no account.

One GATE CSE PYQ every morning

An official question by email at 7 AM IST, with a link to its verified solution. Unsubscribe in one click.

Code Generation in GATE CSE

GATE CSE 2013 Q49 is the only Code Generation question in the GATE CSE papers so far.

How GATE tests Code Generation

More from GATE CSE 2013

Share this solution

A plain-text card for WhatsApp or Telegram study groups.

GateAI solution cardGATE CSE 2013 · Q49 · MCQ

Common Data for Questions 48 and 49: The following code segment is executed on a processor which allows only register operands in its instructions. Each instruction can have atmost two source operands and one destination operand. Assume that all variables are dead after this code segment. c = a + b; d = c * a; e = c + a; x = c * c; if (x > a) { y = a * a; } else { d = d * d; e = e * e; } What is the minimum number of registers needed in the instruction set architecture of the processor to compile this code segment without any spill to memory? Do not apply any optimization other than optimizing register allocation.

Topic-wise GATE CS PYQs with verified steps

Independent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.