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Memory Management and Virtual Memory

GATE CSE 2013 · Q52

MCQ2 marksMedium

Time

Statement for Linked Answer Questions 52 and 53

A computer uses 46-bit virtual address, 32-bit physical address, and a three-level paged page table organization. The page table base register stores the base address of the first-level table (T1T_1), which occupies exactly one page. Each entry of T1T_1 stores the base address of a page of the second-level table (T2T_2). Each entry of T2T_2 stores the base address of a page of the third-level table (T3T_3). Each entry of T3T_3 stores a page table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16-way set associative virtually indexed physically tagged cache. The cache block size is 64 bytes. What is the size of a page in KB in this computer?

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Official answer: C) 8

Memory Management and Virtual Memory

Let the page size be P=2pP = 2^p bytes. The page offset requires pp bits.

The size of a Page Table Entry (PTE) is given as 32 bits =4 bytes=22 bytes= 4\text{ bytes} = 2^2\text{ bytes}.

The number of entries per page in each level of the page table is:

Entries per page=2p22=2p−2\text{Entries per page} = \frac{2^p}{2^2} = 2^{p-2}

Thus, each level of the page table requires (p−2)(p - 2) bits to index its entries.

In a 3-level page table scheme, the virtual address is divided into:

Virtual Address=Index(T1)+Index(T2)+Index(T3)+Page Offset\text{Virtual Address} = \text{Index}(T_1) + \text{Index}(T_2) + \text{Index}(T_3) + \text{Page Offset}

Given that the total virtual address length is 46 bits:

(p−2)+(p−2)+(p−2)+p=46(p - 2) + (p - 2) + (p - 2) + p = 46
4p−6=464p - 6 = 46
4p=52  ⟹  p=134p = 52 \implies p = 13

Therefore, the page size is:

213 bytes=8192 bytes=8 KB2^{13}\text{ bytes} = 8192\text{ bytes} = 8\text{ KB}

Hence, the correct option is (C).

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This Memory Management and Virtual Memory previous year question is Q52 of the GATE CSE 2013 paper. Find more GATE CSE PYQs on Memory Management and Virtual Memory in Operating Systems, or browse all GATE CSE PYQs.

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Memory Management and Virtual Memory in GATE CSE

Memory Management and Virtual Memory has 32 GATE CSE PYQs across 22 papers from 2011 to 2026. 6 of them are 2-mark MCQs like this one, and it is the only one in GATE CSE 2013.

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GateAI solution cardGATE CSE 2013 · Q52 · MCQ

Statement for Linked Answer Questions 52 and 53: A computer uses 46-bit virtual address, 32-bit physical address, and a three-level paged page table organization. The page table base register stores the base address of the first-level table (T1), which occupies exactly one page. Each entry of T1 stores the base address of a page of the second-level table (T2). Each entry of T2 stores the base address of a page of the third-level table (T3). Each entry of T3 stores a page table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16-way set associative virtually indexed physically tagged cache. The cache block size is 64 bytes. What is the size of a page in KB in this computer?

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