A RAM chip has a capacity of 1024 words of 8 bits each ($1\text{K} \times 8$). The number of $2 \times 4$ decoders with enable line needed to construct a $16\text{K} \times 16$ RAM from $1\text{K} \times 8$ RAM is

1. Total Number of Chips Required:

   $$\text{Number of RAM chips} = \frac{16\text{K} \times 16}{1\text{K} \times 8} = \frac{16\text{K}}{1\text{K}} \times \frac{16}{8} = 16 \times 2 = 32\text{ chips}$$

2. RAM Array Organization:

   • The chips are arranged in a 2D matrix of $16$ rows $\times 2$ columns.

   • Each row provides $1\text{K} \times 16$ bits of memory, so $16$ rows provide $16\text{K} \times 16$ bits.

3. Address Decoding:

   • To select one of the $16$ rows, a $4 \times 16$ decoder is needed (since $2^4 = 16$).

4. Constructing a $4 \times 16$ Decoder Using $2 \times 4$ Decoders:

   • First Level: $1$ decoder of size $2 \times 4$ to decode the two most significant address bits.

   • Second Level: $4$ decoders of size $2 \times 4$ (each enabled by one of the $4$ outputs of the first-level decoder) to decode the two least significant address bits.

   • Total $2 \times 4$ decoders required:

     $$1 + 4 = 5$$

Hence, the correct option is (B).