A RAM chip has a capacity of 1024 words of 8 bits each (1K 8). The number of 2 4 decoders with enable line needed to construct a 16K 16 RAM from 1K 8 RAM is A) 4 B) 5 C) 6 D) 7

Official answer: B) 5. Explanation: 1. Total Number of Chips Required: Number of RAM chips = 16K 161K 8 = 16K1K 168 = 16 2 = 32 chips 2. RAM Array Organization: - The chips are arranged in a 2D matrix of 16 rows 2 columns. - Each row provides 1K 16 bits of memory, so 16 rows provide 16K 16 bits. 3. Address Decoding: - To select one of the 16 rows, a 4 16 decoder is needed (since 24 = 16). 4. Constructing a 4 16 Decoder Using 2 4 Decoders: - First Level: 1 decoder of size 2 4 to decode the two most significant address bits. - Second Level: 4 decoders of size 2 4 (each enabled by one of the 4 outputs of the first-level decoder) to decode the two least significant address bits. - Total 2 4 decoders required: 1 + 4 = 5 Hence, the correct option is (B).

Computer Organization and Architecture · Cache Memory and Hierarchy

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GATE CSE 2013 Q46 · MCQ · 2 marks

A RAM chip has a capacity of 1024 words of 8 bits each ( $1\text{K} \times 8$ ). The number of $2 \times 4$ decoders with enable line needed to construct a $16\text{K} \times 16$ RAM from $1\text{K} \times 8$ RAM is

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Cache Memory and Hierarchy

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How GATE tests Cache Memory and Hierarchy

Memory hierarchy and cache mapping is one of the highest-yield, most quantitative topics in GATE Computer Science, regularly tested through 2-mark NAT and MSQ questions. GATE focuses heavily on bit-level address field decomposition (Tag, Set/Line Index, Block Offset) across direct, set-associative, and fully-associative caches, as well as multi-level hierarchical Average Memory Access Time (AMAT) calculations. Recent years have increased the emphasis on multi-select questions (MSQs) tracing reference sequences for eviction behavior and comparing write-back versus write-through policies.

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Computer Organization and Architecture · Cache Memory and Hierarchy

Official IIT answer key · IIT Bombay · Audited Aug 2026

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GATE CSE 2013 Q46 · MCQ · 2 marks

A RAM chip has a capacity of 1024 words of 8 bits each ( $1\text{K} \times 8$ ). The number of $2 \times 4$ decoders with enable line needed to construct a $16\text{K} \times 16$ RAM from $1\text{K} \times 8$ RAM is

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Key concept

Cache Memory and Hierarchy

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Examiner trap & misconception

Topic notes

How GATE tests Cache Memory and Hierarchy

Full Cache Memory and Hierarchy guide →

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All 47 questions on Cache Memory and Hierarchy →

Independent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.

A RAM chip has a capacity of 1024 words of 8 bits each ( $1\text{K} \times 8$ ). The number of $2 \times 4$ decoders with enable line needed to construct a $16\text{K} \times 16$ RAM from $1\text{K} \times 8$ RAM is

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A RAM chip has a capacity of 1024 words of 8 bits each ( $1\text{K} \times 8$ ). The number of $2 \times 4$ decoders with enable line needed to construct a $16\text{K} \times 16$ RAM from $1\text{K} \times 8$ RAM is

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A RAM chip has a capacity of 1024 words of 8 bits each (1K×81\text{K} \times 81K×8). The number of 2×42 \times 42×4 decoders with enable line needed to construct a 16K×1616\text{K} \times 1616K×16 RAM from 1K×81\text{K} \times 81K×8 RAM is

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A RAM chip has a capacity of 1024 words of 8 bits each (1K×81\text{K} \times 81K×8). The number of 2×42 \times 42×4 decoders with enable line needed to construct a 16K×1616\text{K} \times 1616K×16 RAM from 1K×81\text{K} \times 81K×8 RAM is

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A RAM chip has a capacity of 1024 words of 8 bits each ( $1\text{K} \times 8$ ). The number of $2 \times 4$ decoders with enable line needed to construct a $16\text{K} \times 16$ RAM from $1\text{K} \times 8$ RAM is

A RAM chip has a capacity of 1024 words of 8 bits each ( $1\text{K} \times 8$ ). The number of $2 \times 4$ decoders with enable line needed to construct a $16\text{K} \times 16$ RAM from $1\text{K} \times 8$ RAM is