The minimum number of JK flip-flops required to construct a synchronous counter with the count sequence (0,0,1,1,2,2,3,3,0,0, ) is …
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GATE CSE 2015 Set 2 · Q7
Time
Your answerNumerical answer
Solution
Official answer: 3
Combinational and Sequential CircuitsThe counter cycles through the sequence .
Since each output state appears twice, the circuit needs distinct internal states to differentiate the first occurrence from the second occurrence of each number (e.g., and ).
Total number of unique states .
The minimum number of flip-flops required satisfies:
Therefore, a minimum of 3 JK flip-flops are required.
Try the question first, then check your work.
Examiner trap
Count the total number of states in one full repeating period of the sequence.
This Combinational and Sequential Circuits previous year question is Q7 of the GATE CSE 2015 Set 2 paper. Find more GATE CSE PYQs on Combinational and Sequential Circuits in Digital Logic, or browse all GATE CSE PYQs.
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Combinational and Sequential Circuits has 32 GATE CSE PYQs across 22 papers from 2011 to 2026. 6 of them are 1-mark NAT questions like this one, and it is the only one in GATE CSE 2015 Set 2.
How GATE tests Combinational and Sequential CircuitsIndependent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.