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Combinational and Sequential Circuits

GATE CSE 2015 Set 2 · Q7

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The minimum number of JK flip-flops required to construct a synchronous counter with the count sequence (0,0,1,1,2,2,3,3,0,0,…)(0,0,1,1,2,2,3,3,0,0,\ldots) is ______.

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Official answer: 3

Combinational and Sequential Circuits

The counter cycles through the sequence (0,0,1,1,2,2,3,3)(0, 0, 1, 1, 2, 2, 3, 3).

Since each output state appears twice, the circuit needs distinct internal states to differentiate the first occurrence from the second occurrence of each number (e.g., 0a→0b0_a \to 0_b and 0b→1a0_b \to 1_a).

  • Total number of unique states N=8N = 8.

  • The minimum number of flip-flops nn required satisfies:

    2n≥N  ⟹  2n≥8  ⟹  n=32^n \ge N \implies 2^n \ge 8 \implies n = 3

Therefore, a minimum of 3 JK flip-flops are required.

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This Combinational and Sequential Circuits previous year question is Q7 of the GATE CSE 2015 Set 2 paper. Find more GATE CSE PYQs on Combinational and Sequential Circuits in Digital Logic, or browse all GATE CSE PYQs.

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Combinational and Sequential Circuits in GATE CSE

Combinational and Sequential Circuits has 32 GATE CSE PYQs across 22 papers from 2011 to 2026. 6 of them are 1-mark NAT questions like this one, and it is the only one in GATE CSE 2015 Set 2.

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The minimum number of JK flip-flops required to construct a synchronous counter with the count sequence (0,0,1,1,2,2,3,3,0,0, ) is …

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