A positive edge-triggered D flip-flop is connected to a positive edge-triggered JK flip-flop as follows. The $Q$ output of the D flip-flop is connected to both the J and K inputs of the JK flip-flop, while the $Q$ output of the JK flip-flop is connected to the input of the D flip-flop. Initially, the output of the D flip-flop is set to logic one and the output of the JK flip-flop is cleared. Which one of the following is the bit sequence (including the initial state) generated at the $Q$ output of the JK flip-flop when the flip-flops are connected to a free-running common clock? Assume that J = K = 1 is the toggle mode and J = K = 0 is the state-holding mode of the JK flip-flop. Both the flip-flops have non-zero propagation delays.

Let $Q_D$ and $Q_{JK}$ denote the outputs of the D flip-flop and JK flip-flop, respectively.

From the circuit connections:

• $D = Q_{JK}$

• $J = K = Q_D$

Next state characteristic equations:

• $Q_D^+ = D = Q_{JK}$

• $Q_{JK}^+ = \begin{cases} Q_{JK}, & \text{if } J = K = 0 \\ \overline{Q_{JK}}, & \text{if } J = K = 1 \end{cases}$

Initial State ($t = 0$):

• $Q_D(0) = 1$

• $Q_{JK}(0) = 0$

Tracing state transitions $(Q_D, Q_{JK})$ at each clock pulse:

1. Clock 1:

   • Inputs: $D = 0$, $J = K = 1$

   • Next states: $Q_D = 0$, $Q_{JK} = \overline{0} = 1$

2. Clock 2:

   • Inputs: $D = 1$, $J = K = 0$

   • Next states: $Q_D = 1$, $Q_{JK} = 1$ (holds previous value)

3. Clock 3:

   • Inputs: $D = 1$, $J = K = 1$

   • Next states: $Q_D = 1$, $Q_{JK} = \overline{1} = 0$

4. Clock 4:

   • Inputs: $D = 0$, $J = K = 1$

   • Next states: $Q_D = 0$, $Q_{JK} = 1$

The state sequence $(Q_D, Q_{JK})$ is $(1,0) \to (0,1) \to (1,1) \to (1,0) \to (0,1) \dots$

Thus, the sequence generated at $Q_{JK}$ starting from the initial state is 0110110..., corresponding to option A [19].