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Memory Management and Virtual Memory

GATE CSE 2026 Set 2 · Q54

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A system has a Translation Lookaside Buffer (TLB) that has a reach of 1 MB. TLB reach is defined as the total amount of physical memory that can be accessed through the TLB entries. The paging system uses pages of size 4 KB. The virtual address space is 64 GB and physical address space is 1 GB. If each TLB entry stores a 4-bit process id, page number, frame number, and a 2-bit control field, then the size of the TLB (in bytes) is ________. (answer in integer)

Note: 1K=2102^{10}, 1M=2202^{20}, 1G=2302^{30}

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Official answer: 1536

Memory Management and Virtual Memory

  1. Number of TLB Entries:

    TLB Reach=(Number of TLB entries)×(Page size)\text{TLB Reach} = (\text{Number of TLB entries}) \times (\text{Page size})
    Number of entries=1 MB4 KB=220 B212 B=28=256 entries\text{Number of entries} = \frac{1\text{ MB}}{4\text{ KB}} = \frac{2^{20}\text{ B}}{2^{12}\text{ B}} = 2^8 = 256\text{ entries}

  2. Virtual Address and Page Number bits:

    • Virtual Address Space = 64 GB=236 bytes  ⟹  36 bits64\text{ GB} = 2^{36}\text{ bytes} \implies 36\text{ bits}

    • Page size = 4 KB=212 bytes  ⟹  Page offset=12 bits4\text{ KB} = 2^{12}\text{ bytes} \implies \text{Page offset} = 12\text{ bits}

    • Page number bits=36−12=24 bits\text{Page number bits} = 36 - 12 = 24\text{ bits}

  3. Physical Address and Frame Number bits:

    • Physical Address Space = 1 GB=230 bytes  ⟹  30 bits1\text{ GB} = 2^{30}\text{ bytes} \implies 30\text{ bits}

    • Frame number bits=30−12=18 bits\text{Frame number bits} = 30 - 12 = 18\text{ bits}

  4. Size of each TLB Entry:

    Entry size=Process ID+Page number+Frame number+Control bits\text{Entry size} = \text{Process ID} + \text{Page number} + \text{Frame number} + \text{Control bits}
    Entry size=4+24+18+2=48 bits=6 bytes\text{Entry size} = 4 + 24 + 18 + 2 = 48\text{ bits} = 6\text{ bytes}

  5. Total TLB Size:

    TLB size=256×6 bytes=1536 bytes\text{TLB size} = 256 \times 6\text{ bytes} = 1536\text{ bytes}

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This Memory Management and Virtual Memory previous year question is Q54 of the GATE CSE 2026 Set 2 paper. Find more GATE CSE PYQs on Memory Management and Virtual Memory in Operating Systems, or browse all GATE CSE PYQs.

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Memory Management and Virtual Memory in GATE CSE

Memory Management and Virtual Memory has 32 GATE CSE PYQs across 22 papers from 2011 to 2026. 15 of them are 2-mark NAT questions like this one, and GATE CSE 2026 Set 2 has 2.

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GateAI solution cardGATE CSE 2026 Set 2 · Q54 · NAT

A system has a Translation Lookaside Buffer (TLB) that has a reach of 1 MB. TLB reach is defined as the total amount of physical memory that can be accessed through the TLB entries. The paging system uses pages of size 4 KB. The virtual address space is 64 GB and physical address space is 1 GB. If each TLB entry stores a 4-bit process id, page number, frame number, and a 2-bit control field, then the size of the TLB (in bytes) is … (answer in integer) Note: 1K=210, 1M=220, 1G=230

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