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Instruction Pipelining

GATE CSE 2026 Set 2 · Q57

NAT2 marksMedium

Time

A non-pipelined instruction execution unit that operates at 1.6 GHz clock takes an average of 5 clock cycles to complete the execution of an instruction. To improve the performance, the system was pipelined with a goal of achieving an average throughput of one instruction per clock cycle. However, it could operate only at 1.2 GHz due to pipeline overheads. While executing a program in the pipelined design, 30% of instructions encountered a stall of 2 cycles due to pipeline hazards. The speed-up obtained by the pipelined design over the non-pipelined one for this program is ________. (rounded off to two decimal places)

Note: 1G=10910^9

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Official answer: 2.34 (±0.06) (±0.06)

Instruction Pipelining
  1. Execution Time for Non-Pipelined System:

    • Clock frequency fnp=1.6 GHzf_{\text{np}} = 1.6\text{ GHz}

    • Cycle time Tnp=11.6×109 sT_{\text{np}} = \frac{1}{1.6 \times 10^9}\text{ s}

    • Average CPInp=5\text{CPI}_{\text{np}} = 5

    • Average execution time per instruction:

      tnp=CPInp×Tnp=51.6×109 st_{\text{np}} = \text{CPI}_{\text{np}} \times T_{\text{np}} = \frac{5}{1.6 \times 10^9}\text{ s}
  2. Execution Time for Pipelined System:

    • Clock frequency fp=1.2 GHzf_{\text{p}} = 1.2\text{ GHz}

    • Cycle time Tp=11.2×109 sT_{\text{p}} = \frac{1}{1.2 \times 10^9}\text{ s}

    • Base CPI=1\text{CPI} = 1

    • Stall cycles per instruction =0.30×2=0.6= 0.30 \times 2 = 0.6

    • Average CPIp=1+0.6=1.6\text{CPI}_{\text{p}} = 1 + 0.6 = 1.6

    • Average execution time per instruction:

      tp=CPIp×Tp=1.61.2×109 st_{\text{p}} = \text{CPI}_{\text{p}} \times T_{\text{p}} = \frac{1.6}{1.2 \times 10^9}\text{ s}
  3. Speed-up Calculation:

    Speed-up=tnptp=51.6×1091.61.2×109=5×1.21.6×1.6=6.02.56≈2.34375\text{Speed-up} = \frac{t_{\text{np}}}{t_{\text{p}}} = \frac{\frac{5}{1.6 \times 10^9}}{\frac{1.6}{1.2 \times 10^9}} = \frac{5 \times 1.2}{1.6 \times 1.6} = \frac{6.0}{2.56} \approx 2.34375

Rounding off to two decimal places gives 2.34.

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This Instruction Pipelining previous year question is Q57 of the GATE CSE 2026 Set 2 paper. Find more GATE CSE PYQs on Instruction Pipelining in Computer Organization and Architecture, or browse all GATE CSE PYQs.

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Instruction Pipelining in GATE CSE

Instruction Pipelining has 25 GATE CSE PYQs across 20 papers from 2011 to 2026. 16 of them are 2-mark NAT questions like this one, and it is the only one in GATE CSE 2026 Set 2.

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GateAI solution cardGATE CSE 2026 Set 2 · Q57 · NAT

A non-pipelined instruction execution unit that operates at 1.6 GHz clock takes an average of 5 clock cycles to complete the execution of an instruction. To improve the performance, the system was pipelined with a goal of achieving an average throughput of one instruction per clock cycle. However, it could operate only at 1.2 GHz due to pipeline overheads. While executing a program in the pipelined design, 30% of instructions encountered a stall of 2 cycles due to pipeline hazards. The speed-up obtained by the pipelined design over the non-pipelined one for this program is … (rounded off to two decimal places) Note: 1G=109

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