Computer Organization and Architecture · Cache Memory and Hierarchy
Official IIT answer key · IIT Roorkee · Audited Aug 2026
GATE CSE 2026 Set 2 Q56 · NAT · 2 marks
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Topic notes
Memory hierarchy and cache mapping is one of the highest-yield, most quantitative topics in GATE Computer Science, regularly tested through 2-mark NAT and MSQ questions. GATE focuses heavily on bit-level address field decomposition (Tag, Set/Line Index, Block Offset) across direct, set-associative, and fully-associative caches, as well as multi-level hierarchical Average Memory Access Time (AMAT) calculations. Recent years have increased the emphasis on multi-select questions (MSQs) tracing reference sequences for eviction behavior and comparing write-back versus write-through policies.
Full Cache Memory and Hierarchy guide →Consider a system with 1 MB physical memory and a word length of 1 byte. The system uses a direct mapped cache, with block numbers starting from 0. The word with physical address 0xA2C28 is mapped to the cache block number 17610. The maximum possible size of the cache (in KB) for this configuration is … (answer in integer) Note: 1K=210 and 1M=220
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