Compiler Design · Intermediate Code Generation
Official IIT answer key · IIT Roorkee · Audited Aug 2026
GATE CSE 2017 Set 1 Q52 · NAT · 2 marks
Key concept
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Topic notes
In GATE CS, Intermediate Code Generation (ICG) is tested through both theoretical/architectural concepts and precise algorithmic computations. Core recurring topics include Static Single Assignment (SSA) form variable counting and renaming, basic block partitioning via leader identification, register allocation on expression trees (Sethi-Ullman / Ershov labeling), array address calculation in 3-address code, and IR structures (Triples, AST, CFG, backpatching). The topic maintains an even split between 1-mark conceptual questions and 2-mark procedural NAT/MCQ problems.
Full Intermediate Code Generation guide →Consider the expression (a - 1) * (((b + c) / 3) + d). Let X be the minimum number of registers required by an optimal code generation (without any register spill) algorithm for a load/store architecture, in which (i) only load and store instructions can have memory operands and (ii) arithmetic instructions can have only register or immediate operands. The value of X is …
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Independent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.
