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Intermediate Code Generation

GATE CSE 2017 Set 1 · Q52

NAT2 marksMedium

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Consider the expression (a−1)∗(((b+c)/3)+d)(a - 1) * (((b + c) / 3) + d). Let X be the minimum number of registers required by an optimal code generation (without any register spill) algorithm for a load/store architecture, in which (i) only load and store instructions can have memory operands and (ii) arithmetic instructions can have only register or immediate operands. The value of X is _________.

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Official answer: 2 (±0)

Intermediate Code Generation

We are evaluating the expression:

E=(a−1)∗(((b+c)/3)+d)E = (a - 1) * (((b + c) / 3) + d)

Let's determine the minimum number of registers required using optimal evaluation order (evaluating the heavier subtree first):

  1. Evaluate the right operand (((b+c)/3)+d)(((b+c)/3)+d) first:

    • LOAD R1, b (R1 = b)

    • LOAD R2, c (R2 = c)

    • ADD R1, R1, R2 (R1 = b + c, R2 becomes free)

    • DIV R1, R1, 3 (R1 = (b + c) / 3, immediate operand)

    • LOAD R2, d (R2 = d)

    • ADD R1, R1, R2 (R1 = ((b + c) / 3) + d, R2 becomes free)

  2. Evaluate the left operand (a−1)(a - 1):

    • LOAD R2, a (R2 = a)

    • SUB R2, R2, 1 (R2 = a - 1, immediate operand)

  3. Perform the final multiplication:

    • MUL R1, R2, R1 (R1 = (a - 1) * (((b + c) / 3) + d))

Throughout the computation, only 22 registers (R1R_1 and R2R_2) are used simultaneously with no register spilling. Since at least 22 registers are required to hold the operands for the binary multiplication operator, the minimum number of registers is 2.

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This Intermediate Code Generation previous year question is Q52 of the GATE CSE 2017 Set 1 paper. Find more GATE CSE PYQs on Intermediate Code Generation in Compiler Design, or browse all GATE CSE PYQs.

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Intermediate Code Generation in GATE CSE

Intermediate Code Generation has 14 GATE CSE PYQs across 12 papers from 2011 to 2025. 3 of them are 2-mark NAT questions like this one, and GATE CSE 2017 Set 1 has 3.

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GateAI solution cardGATE CSE 2017 Set 1 · Q52 · NAT

Consider the expression (a - 1) * (((b + c) / 3) + d). Let X be the minimum number of registers required by an optimal code generation (without any register spill) algorithm for a load/store architecture, in which (i) only load and store instructions can have memory operands and (ii) arithmetic instructions can have only register or immediate operands. The value of X is …

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Independent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.