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Cache Memory and Hierarchy

GATE CSE 2017 Set 1 · Q54

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A cache memory unit with capacity of NN words and block size of BB words is to be designed. If it is designed as a direct mapped cache, the length of the TAG field is 10 bits. If the cache unit is now designed as a 16-way set-associative cache, the length of the TAG field is _________ bits.

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Official answer: 14 (±0)

Cache Memory and Hierarchy

Let the main memory physical address have AA bits.

  1. Direct-Mapped Cache:

    • Cache capacity =N= N words

    • Block size =B= B words

    • Number of cache lines/blocks =NB= \frac{N}{B}

    • Block offset bits =log⁡2(B)= \log_2(B)

    • Line index bits =log⁡2(NB)=log⁡2(N)−log⁡2(B)= \log_2\left(\frac{N}{B}\right) = \log_2(N) - \log_2(B)

    • Tag bitsdirect=A−(Line index bits+Block offset bits)=A−log⁡2(N)\text{Tag bits}_{\text{direct}} = A - (\text{Line index bits} + \text{Block offset bits}) = A - \log_2(N)

    • Given Tag bitsdirect=10\text{Tag bits}_{\text{direct}} = 10, so:

      A−log⁡2(N)=10A - \log_2(N) = 10
  2. 16-way Set-Associative Cache:

    • Set size =16= 16 blocks/set

    • Number of sets =Total blocks16=N/B16=N16B= \frac{\text{Total blocks}}{16} = \frac{N/B}{16} = \frac{N}{16B}

    • Set index bits =log⁡2(N16B)=log⁡2(N)−log⁡2(B)−4= \log_2\left(\frac{N}{16B}\right) = \log_2(N) - \log_2(B) - 4

    • Block offset bits =log⁡2(B)= \log_2(B)

    • Tag bitsset-assoc=A−(Set index bits+Block offset bits)\text{Tag bits}_{\text{set-assoc}} = A - (\text{Set index bits} + \text{Block offset bits})

      Tag bitsset-assoc=A−(log⁡2(N)−4)=(A−log⁡2(N))+4\text{Tag bits}_{\text{set-assoc}} = A - (\log_2(N) - 4) = (A - \log_2(N)) + 4

Substituting $A - \log_2(N) = 10$:

Tag bitsset-assoc=10+4=14\text{Tag bits}_{\text{set-assoc}} = 10 + 4 = 14

Thus, the length of the TAG field is 14 bits.

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This Cache Memory and Hierarchy previous year question is Q54 of the GATE CSE 2017 Set 1 paper. Find more GATE CSE PYQs on Cache Memory and Hierarchy in Computer Organization and Architecture, or browse all GATE CSE PYQs.

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Cache Memory and Hierarchy in GATE CSE

Cache Memory and Hierarchy has 47 GATE CSE PYQs across 23 papers from 2011 to 2026. 16 of them are 2-mark NAT questions like this one, and GATE CSE 2017 Set 1 has 3.

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GateAI solution cardGATE CSE 2017 Set 1 · Q54 · NAT

A cache memory unit with capacity of N words and block size of B words is to be designed. If it is designed as a direct mapped cache, the length of the TAG field is 10 bits. If the cache unit is now designed as a 16-way set-associative cache, the length of the TAG field is … bits.

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Independent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.