Instruction execution in a processor is divided into 5 stages, Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Execute (EX), and Write Back (WB). These stages take 5, 4, 20, 10, and 3 nanoseconds (ns) respectively. A pipelined implementation of the processor requires buffering between each pair of consecutive stages with a delay of 2 ns. Two pipelined implementations of the processor are contemplated: (i) a naive pipeline implementation (NP) with 5 stages and (ii) an efficient pipeline (EP) where the OF stage is divided into stages OF1 and OF2 with execution times of 12 ns and 8 ns respectively. The speedup (correct to two decimal places) achieved by EP over NP in executing 20 independent instructions with no hazards is _________.

To find the speedup achieved by the Efficient Pipeline (EP) over the Naive Pipeline (NP) for $n = 20$ instructions:

### 1. Naive Pipeline (NP):

• Number of stages, $k_{NP} = 5$ (IF, ID, OF, EX, WB) with delays 5, 4, 20, 10, 3 ns respectively.

• Buffer delay $= 2\text{ ns}$.

• Clock cycle time, $t_{NP} = \max(5, 4, 20, 10, 3) + 2 = 20 + 2 = 22\text{ ns}$.

• Total execution time for $n = 20$ instructions:

### 2. Efficient Pipeline (EP):

• Number of stages, $k_{EP} = 6$ (IF, ID, OF1, OF2, EX, WB) with delays 5, 4, 12, 8, 10, 3 ns respectively.

• Buffer delay $= 2\text{ ns}$.

• Clock cycle time, $t_{EP} = \max(5, 4, 12, 8, 10, 3) + 2 = 12 + 2 = 14\text{ ns}$.

• Total execution time for $n = 20$ instructions:

### 3. Speedup:

Thus, the speedup achieved is 1.51 (acceptable range: 1.49 to 1.52).