The minimum number of D flip-flops needed to design a mod-258 counter is

GATE extensively tests combinational and sequential circuit design through both analytical tracing and formal synthesis. In combinational circuits, questions focus on multiplexer tree implementations, decoder-to-memory interfacing, and Boolean function realization using universal MUX/decoder blocks. In sequential logic, the focus is on synchronous counter state tracing, excitation equation derivation (for D, T, and JK flip-flops), non-standard sequence flip-flop counting, ripple counter frequency division, and FSM equivalence minimization.