The above synchronous sequential circuit built using JK flip-flops is initialized with Q2Q1Q0 = 000. The state sequence for this circuit for the next 3 clock cycles is
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GATE CSE 2014 Set 3 · Q45
Time

Select one answerSingle correct
Solution
Official answer: C) 100, 110, 111
Combinational and Sequential CircuitsFrom the circuit diagram, the inputs to the JK flip-flops are connected as follows:
Flip-flop 2 ():
Characteristic equation:
Flip-flop 1 ():
Characteristic equation:
Flip-flop 0 ():
Characteristic equation:
Now, tracking the state transitions starting from :
Clock Cycle 1:
Current state:
Inputs:
Inputs:
Inputs:
Next State 1:
Clock Cycle 2:
Current state:
Inputs:
Inputs:
Inputs:
Next State 2:
Clock Cycle 3:
Current state:
Inputs:
Inputs:
Inputs:
Next State 3:
Thus, the state sequence for the next 3 clock cycles is 100, 110, 111, which corresponds to option (C).
Try the question first, then check your work.
Examiner trap
Derive the input equations for and for each flip-flop and evaluate the next state step-by-step starting from state .
This Combinational and Sequential Circuits previous year question is Q45 of the GATE CSE 2014 Set 3 paper. Find more GATE CSE PYQs on Combinational and Sequential Circuits in Digital Logic, or browse all GATE CSE PYQs.
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Combinational and Sequential Circuits has 32 GATE CSE PYQs across 22 papers from 2011 to 2026. 14 of them are 2-mark MCQs like this one, and GATE CSE 2014 Set 3 has 2.
How GATE tests Combinational and Sequential CircuitsIndependent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.