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Combinational and Sequential Circuits

GATE CSE 2014 Set 3 · Q45

MCQ2 marksMedium

Time

The above synchronous sequential circuit built using JK flip-flops is initialized with Q2Q1Q0=000Q_2Q_1Q_0 = 000. The state sequence for this circuit for the next 3 clock cycles is

GATE CSE 2014 Set 3 Q45 diagram

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Solution

Step-by-step verified solution

Official answer: C) 100, 110, 111

Combinational and Sequential Circuits

From the circuit diagram, the inputs to the JK flip-flops are connected as follows:

  • Flip-flop 2 (Q2Q_2):

    J2=Q‾0,K2=Q‾0J_2 = \overline{Q}_0, \quad K_2 = \overline{Q}_0

    Characteristic equation: Q2+=J2Q‾2+K‾2Q2=Q‾0Q‾2+Q0Q2Q_2^+ = J_2 \overline{Q}_2 + \overline{K}_2 Q_2 = \overline{Q}_0 \overline{Q}_2 + Q_0 Q_2

  • Flip-flop 1 (Q1Q_1):

    J1=Q2,K1=Q‾2J_1 = Q_2, \quad K_1 = \overline{Q}_2

    Characteristic equation: Q1+=J1Q‾1+K‾1Q1=Q2Q‾1+Q2Q1=Q2Q_1^+ = J_1 \overline{Q}_1 + \overline{K}_1 Q_1 = Q_2 \overline{Q}_1 + Q_2 Q_1 = Q_2

  • Flip-flop 0 (Q0Q_0):

    J0=Q1,K0=Q‾1J_0 = Q_1, \quad K_0 = \overline{Q}_1

    Characteristic equation: Q0+=J0Q‾0+K‾0Q0=Q1Q‾0+Q1Q0=Q1Q_0^+ = J_0 \overline{Q}_0 + \overline{K}_0 Q_0 = Q_1 \overline{Q}_0 + Q_1 Q_0 = Q_1

Now, tracking the state transitions starting from Q2Q1Q0=000Q_2 Q_1 Q_0 = 000:

  1. Clock Cycle 1:

    • Current state: Q2Q1Q0=000Q_2 Q_1 Q_0 = 000

    • Inputs: J2=1,K2=1  ⟹  Q2+=1J_2=1, K_2=1 \implies Q_2^+ = 1

    • Inputs: J1=0,K1=1  ⟹  Q1+=0J_1=0, K_1=1 \implies Q_1^+ = 0

    • Inputs: J0=0,K0=1  ⟹  Q0+=0J_0=0, K_0=1 \implies Q_0^+ = 0

    • Next State 1: 100100

  2. Clock Cycle 2:

    • Current state: Q2Q1Q0=100Q_2 Q_1 Q_0 = 100

    • Inputs: J2=1,K2=1  ⟹  Q2+=1J_2=1, K_2=1 \implies Q_2^+ = 1

    • Inputs: J1=1,K1=0  ⟹  Q1+=1J_1=1, K_1=0 \implies Q_1^+ = 1

    • Inputs: J0=0,K0=1  ⟹  Q0+=0J_0=0, K_0=1 \implies Q_0^+ = 0

    • Next State 2: 110110

  3. Clock Cycle 3:

    • Current state: Q2Q1Q0=110Q_2 Q_1 Q_0 = 110

    • Inputs: J2=1,K2=1  ⟹  Q2+=1J_2=1, K_2=1 \implies Q_2^+ = 1

    • Inputs: J1=1,K1=0  ⟹  Q1+=1J_1=1, K_1=0 \implies Q_1^+ = 1

    • Inputs: J0=1,K0=0  ⟹  Q0+=1J_0=1, K_0=0 \implies Q_0^+ = 1

    • Next State 3: 111111

Thus, the state sequence for the next 3 clock cycles is 100, 110, 111, which corresponds to option (C).

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This Combinational and Sequential Circuits previous year question is Q45 of the GATE CSE 2014 Set 3 paper. Find more GATE CSE PYQs on Combinational and Sequential Circuits in Digital Logic, or browse all GATE CSE PYQs.

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Combinational and Sequential Circuits has 32 GATE CSE PYQs across 22 papers from 2011 to 2026. 14 of them are 2-mark MCQs like this one, and GATE CSE 2014 Set 3 has 2.

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The above synchronous sequential circuit built using JK flip-flops is initialized with Q2Q1Q0 = 000. The state sequence for this circuit for the next 3 clock cycles is

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