GateAI
Combinational and Sequential Circuits

GATE CSE 2017 Set 1 · Q33

MCQ2 marksMedium

Time

Consider a combination of T and D flip-flops connected as shown below. The output of the D flip-flop is connected to the input of the T flip-flop and the output of the T flip-flop is connected to the input of the D flip-flop. Initially, both Q0Q_0 and Q1Q_1 are set to 1 (before the 1st1^{\text{st}} clock cycle). The outputs

GATE CSE 2017 Set 1 Q33 diagram

Select one answerSingle correct

Pick an option to check

Solution

Step-by-step verified solution

Official answer: B) Q1 Q0 after the 3rd cycle are 11 and after the 4th cycle are 01 respectively

Combinational and Sequential Circuits

From the circuit diagram:

  • The T flip-flop has input T=Q0T = Q_0 and output Q1Q_1.

  • The D flip-flop has input D=Q1D = Q_1 and output Q0Q_0.

The next-state equations are:

Q1(n+1)=T⊕Q1(n)=Q0(n)⊕Q1(n)Q_1(n+1) = T \oplus Q_1(n) = Q_0(n) \oplus Q_1(n)
Q0(n+1)=D=Q1(n)Q_0(n+1) = D = Q_1(n)

Tracing cycle-by-cycle starting from initial state Q1Q0=11Q_1 Q_0 = 11:

  • Initial (Cycle 0):Q1=1,Q0=1Q_1 = 1, Q_0 = 1

  • Cycle 1:

    Q1(1)=1⊕1=0,Q0(1)=1  ⟹  Q1Q0=01Q_1(1) = 1 \oplus 1 = 0, \quad Q_0(1) = 1 \implies Q_1 Q_0 = 01
  • Cycle 2:

    Q1(2)=1⊕0=1,Q0(2)=0  ⟹  Q1Q0=10Q_1(2) = 1 \oplus 0 = 1, \quad Q_0(2) = 0 \implies Q_1 Q_0 = 10
  • Cycle 3:

    Q1(3)=0⊕1=1,Q0(3)=1  ⟹  Q1Q0=11Q_1(3) = 0 \oplus 1 = 1, \quad Q_0(3) = 1 \implies Q_1 Q_0 = 11
  • Cycle 4:

    Q1(4)=1⊕1=0,Q0(4)=1  ⟹  Q1Q0=01Q_1(4) = 1 \oplus 1 = 0, \quad Q_0(4) = 1 \implies Q_1 Q_0 = 01

Thus, Q1Q0Q_1 Q_0 after the 3rd3^{\text{rd}} cycle is 11 and after the 4th4^{\text{th}} cycle is 01.

Hence, the correct option is B.

Try the question first, then check your work.

Think the official key or this write-up is wrong?

Report error or challenge

Examiner trap

The misconception this question tests

This Combinational and Sequential Circuits previous year question is Q33 of the GATE CSE 2017 Set 1 paper. Find more GATE CSE PYQs on Combinational and Sequential Circuits in Digital Logic, or browse all GATE CSE PYQs.

Free diagnostic

Where do you stand for GATE?

Take the 20-minute diagnostic: the 3 topics that cost you the most marks, and a rank range. Or sit 5 related Combinational and Sequential Circuits PYQs now with no account.

One GATE CSE PYQ every morning

An official question by email at 7 AM IST, with a link to its verified solution. Unsubscribe in one click.

Combinational and Sequential Circuits in GATE CSE

Combinational and Sequential Circuits has 32 GATE CSE PYQs across 22 papers from 2011 to 2026. 14 of them are 2-mark MCQs like this one, and it is the only one in GATE CSE 2017 Set 1.

How GATE tests Combinational and Sequential Circuits

More from GATE CSE 2017 Set 1

Share this solution

A plain-text card for WhatsApp or Telegram study groups.

GateAI solution cardGATE CSE 2017 Set 1 · Q33 · MCQ

Consider a combination of T and D flip-flops connected as shown below. The output of the D flip-flop is connected to the input of the T flip-flop and the output of the T flip-flop is connected to the input of the D flip-flop. Initially, both Q0 and Q1 are set to 1 (before the 1st clock cycle). The outputs

Topic-wise GATE CS PYQs with verified steps

Independent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.