Consider a combination of T and D flip-flops connected as shown below. The output of the D flip-flop is connected to the input of the T flip-flop and the output of the T flip-flop is connected to the input of the D flip-flop. Initially, both Q0 and Q1 are set to 1 (before the 1st clock cycle). The outputs A) Q1 Q0 after the 3rd cycle are 11 and after the 4th cycle are 00 respectively B) Q1 Q0 after the 3rd cycle are 11 and after the 4th cycle are 01 respectively C) Q1 Q0 after the 3rd cycle are 00 and after the 4th cycle are 11 respectively D) Q1 Q0 after the 3rd cycle are 01 and after the 4th cycle are 01 respectively

Official answer: B) Q1 Q0 after the 3rd cycle are 11 and after the 4th cycle are 01 respectively. Explanation: From the circuit diagram: - The T flip-flop has input T = Q0 and output Q1. - The D flip-flop has input D = Q1 and output Q0. The next-state equations are: Q1(n+1) = T Q1(n) = Q0(n) Q1(n) Q0(n+1) = D = Q1(n) Tracing cycle-by-cycle starting from initial state Q1 Q0 = 11: - Initial (Cycle 0): Q1 = 1, Q0 = 1 - Cycle 1: Q1(1) = 1 1 = 0, Q0(1) = 1 Q1 Q0 = 01 - Cycle 2: Q1(2) = 1 0 = 1, Q0(2) = 0 Q1 Q0 = 10 - Cycle 3: Q1(3) = 0 1 = 1, Q0(3) = 1 Q1 Q0 = 11 - Cycle 4: Q1(4) = 1 1 = 0, Q0(4) = 1 Q1 Q0 = 01 Thus, Q1 Q0 after the 3rd cycle is `11` and after the 4th cycle is `01`. Hence, the correct option is B.

A) Q1 Q0 after the 3rd cycle are 11 and after the 4th cycle are 00 respectively

B) Q1 Q0 after the 3rd cycle are 11 and after the 4th cycle are 01 respectively

C) Q1 Q0 after the 3rd cycle are 00 and after the 4th cycle are 11 respectively

D) Q1 Q0 after the 3rd cycle are 01 and after the 4th cycle are 01 respectively

Digital Logic · Combinational and Sequential Circuits

Official IIT answer key · IIT Roorkee · Audited Aug 2026

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GATE CSE 2017 Set 1 Q33 · MCQ · 2 marks

Consider a combination of T and D flip-flops connected as shown below. The output of the D flip-flop is connected to the input of the T flip-flop and the output of the T flip-flop is connected to the input of the D flip-flop. Initially, both $Q_0$ and $Q_1$ are set to 1 (before the $1^{\text{st}}$ clock cycle). The outputs

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Combinational and Sequential Circuits

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How GATE tests Combinational and Sequential Circuits

GATE extensively tests combinational and sequential circuit design through both analytical tracing and formal synthesis. In combinational circuits, questions focus on multiplexer tree implementations, decoder-to-memory interfacing, and Boolean function realization using universal MUX/decoder blocks. In sequential logic, the focus is on synchronous counter state tracing, excitation equation derivation (for D, T, and JK flip-flops), non-standard sequence flip-flop counting, ripple counter frequency division, and FSM equivalence minimization.

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Digital Logic · Combinational and Sequential Circuits

Official IIT answer key · IIT Roorkee · Audited Aug 2026

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GATE CSE 2017 Set 1 Q33 · MCQ · 2 marks

Consider a combination of T and D flip-flops connected as shown below. The output of the D flip-flop is connected to the input of the T flip-flop and the output of the T flip-flop is connected to the input of the D flip-flop. Initially, both $Q_0$ and $Q_1$ are set to 1 (before the $1^{\text{st}}$ clock cycle). The outputs

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Key concept

Combinational and Sequential Circuits

Step-by-step verified solution

Examiner trap & misconception

Topic notes

How GATE tests Combinational and Sequential Circuits

Full Combinational and Sequential Circuits guide →

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Independent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.

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