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Combinational and Sequential Circuits

GATE CSE 2016 Set 1 · Q8

NAT1 markMedium

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We want to design a synchronous counter that counts the sequence 0-1-0-2-0-3 and then repeats. The minimum number of J-K flip-flops required to implement this counter is _________ .

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Solution

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Official answer: 3 (±1) (±1)

Combinational and Sequential Circuits

The required sequence is:

0→1→0→2→0→3→0…0 \to 1 \to 0 \to 2 \to 0 \to 3 \to 0 \dots

There are 66 states in the repeating sequence cycle. Notice that the value 00 appears three times, but is followed by different next values (11, 22, and 33). Therefore, to distinguish each occurrence of 00 and form a deterministic finite state machine (counter), each step in the sequence of length 66 must be assigned a unique state:

  • S0(0)→S1(1)→S2(0)→S3(2)→S4(0)→S5(3)→S0(0)S_0 (0) \to S_1 (1) \to S_2 (0) \to S_3 (2) \to S_4 (0) \to S_5 (3) \to S_0 (0)

The minimum number of distinct states required is N=6N = 6.

The minimum number of flip-flops kk needed to represent NN states is given by:

2k≥N2^k \ge N
2k≥6  ⟹  k=⌈log⁡26⌉=32^k \ge 6 \implies k = \lceil \log_2 6 \rceil = 3

With 33 flip-flops, we can have up to 23=82^3 = 8 distinct states, which is sufficient to encode the 66 states. *(Note: An implementation using 4 flip-flops was also accepted in the official key range of 3 to 4).*

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This Combinational and Sequential Circuits previous year question is Q8 of the GATE CSE 2016 Set 1 paper. Find more GATE CSE PYQs on Combinational and Sequential Circuits in Digital Logic, or browse all GATE CSE PYQs.

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Combinational and Sequential Circuits in GATE CSE

Combinational and Sequential Circuits has 32 GATE CSE PYQs across 22 papers from 2011 to 2026. 6 of them are 1-mark NAT questions like this one, and GATE CSE 2016 Set 1 has 2.

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We want to design a synchronous counter that counts the sequence 0-1-0-2-0-3 and then repeats. The minimum number of J-K flip-flops required to implement this counter is …

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