If there are m input lines and n output lines for a decoder that is used to uniquely address a byte addressable 1 KB RAM, then the minimum value of m + n is …
Topic-wise GATE CS PYQs with verified steps
GATE CSE 2020 · Q20
Time
Your answerNumerical answer
Solution
Official answer: 1034 (±0)
Combinational and Sequential CircuitsFor a byte-addressable RAM:
Total memory capacity .
Since each byte requires a unique address, there are distinct locations to address.
A decoder used to uniquely select one of the locations must have:
Number of output lines, .
Number of input (address) lines, .
Therefore, the minimum value of is:
Try the question first, then check your work.
Examiner trap
A byte-addressable memory has addresses. An -to- decoder decoding these addresses has outputs and inputs.
This Combinational and Sequential Circuits previous year question is Q20 of the GATE CSE 2020 paper. Find more GATE CSE PYQs on Combinational and Sequential Circuits in Digital Logic, or browse all GATE CSE PYQs.
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Combinational and Sequential Circuits has 32 GATE CSE PYQs across 22 papers from 2011 to 2026. 6 of them are 1-mark NAT questions like this one, and GATE CSE 2020 has 2.
How GATE tests Combinational and Sequential CircuitsIndependent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.