Consider a 3-bit counter, designed using T flip-flops, as shown below: Assuming the initial state of the counter given by PQR as 000, what are the next three states?

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Key concept

Combinational and Sequential Circuits

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Examiner trap & misconception

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How GATE tests Combinational and Sequential Circuits

GATE extensively tests combinational and sequential circuit design through both analytical tracing and formal synthesis. In combinational circuits, questions focus on multiplexer tree implementations, decoder-to-memory interfacing, and Boolean function realization using universal MUX/decoder blocks. In sequential logic, the focus is on synchronous counter state tracing, excitation equation derivation (for D, T, and JK flip-flops), non-standard sequence flip-flop counting, ripple counter frequency division, and FSM equivalence minimization.

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Independent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.

Digital Logic · Combinational and Sequential Circuits

Official IIT answer key · IIT Bombay · Audited Aug 2026

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GATE CSE 2021 Set 1 Q28 · MCQ · 2 marks

Consider a 3-bit counter, designed using T flip-flops, as shown below: Assuming the initial state of the counter given by PQR as 000, what are the next three states?

Select an option to check

Key concept

Combinational and Sequential Circuits

Step-by-step verified solution

Examiner trap & misconception

Topic notes

How GATE tests Combinational and Sequential Circuits

Full Combinational and Sequential Circuits guide →

More on Combinational and Sequential Circuits

All 32 questions on Combinational and Sequential Circuits →

Independent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.

Consider a 3-bit counter, designed using T flip-flops, as shown below: Assuming the initial state of the counter given by PQR as 000, what are the next three states?

Step-by-step verified solution

Check you can still solve Combinational and Sequential Circuits under a clock

More from GATE CSE 2021 Set 1

More on Combinational and Sequential Circuits

Consider a 3-bit counter, designed using T flip-flops, as shown below: Assuming the initial state of the counter given by PQR as 000, what are the next three states?

Step-by-step verified solution

Check you can still solve Combinational and Sequential Circuits under a clock

More from GATE CSE 2021 Set 1

More on Combinational and Sequential Circuits

Consider a 3-bit counter, designed using T flip-flops, as shown below: Assuming the initial state of the counter given by PQR as 000, what are the next three states?

Step-by-step verified solution

Check you can still solve Combinational and Sequential Circuits under a clock

More from GATE CSE 2021 Set 1

More on Combinational and Sequential Circuits

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Consider a 3-bit counter, designed using T flip-flops, as shown below: Assuming the initial state of the counter given by PQR as 000, what are the next three states?

Step-by-step verified solution

Check you can still solve Combinational and Sequential Circuits under a clock

More from GATE CSE 2021 Set 1

More on Combinational and Sequential Circuits

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