The output of a 2-input multiplexer is connected back to one of its inputs as shown in the figure. Match the functional equivalence of this circuit to one of the following options.

Let the input at line $1$ be $D$, the select line be $S$, and the output of the multiplexer be $Q$.

The functional equation of a 2-to-1 multiplexer is:

From the given diagram:

• Input $0$ ($I_0$) is connected to the output $Q$ (feedback).

• Input $1$ ($I_1$) is connected to the data input $D$.

• The select line is $S$.

Substituting these into the equation:

• When $S = 0$: $Q_{\text{next}} = Q$ (holds previous state / memory state).

• When $S = 1$: $Q_{\text{next}} = D$ (transparent mode / follows the data input).

Since this circuit is level-sensitive with respect to the control signal $S$, it represents a D Latch (with $S$ acting as the Enable/Clock input).

Therefore, the circuit is functionally equivalent to a D Latch (Option B).

• Option A (D Flip-flop) is incorrect because a flip-flop is edge-triggered, whereas this circuit is level-sensitive without clock edge-triggering circuitry.

• Options C and D are incorrect as the circuit exhibits sequential memory behavior, not the function of a half-adder or demultiplexer.