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Combinational and Sequential Circuits

GATE CSE 2026 Set 1 · Q37

MCQ2 marksMedium

Time

Consider a 2-bit saturating up/down counter that performs the saturating up count when the input PP is 0, and the saturating down count when PP is 1. The Next State table of the counter is as shown. The counter is built as a synchronous sequential circuit using D flip-flops. Which one of the following options corresponds to the expressions for the inputs of the D flip-flops, D1D_1 and D0D_0?

GATE CSE 2026 Set 1 Q37 diagram

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Solution

Step-by-step verified solution

Official answer: B) D1 = P Q1 + P Q0 + Q1 Q0 D0 = P Q0 + P Q1 + Q1 Q0

Combinational and Sequential Circuits

For a D flip-flop, the excitation equation is D=Q+D = Q^+.

From the given Next State table for inputs (P,Q1,Q0)(P, Q_1, Q_0):

  1. For flip-flop D1=Q1+D_1 = Q_1^+:

    • Minterms where $Q_1^+ = 1$: $m(1, 2, 3, 7)$

    • Grouping on a 3-variable K-map:

      • Group 1 (m1,m3m_1, m_3): P‾Q0\overline{P} Q_0

      • Group 2 (m2,m3m_2, m_3): P‾Q1\overline{P} Q_1

      • Group 3 (m3,m7m_3, m_7): Q1Q0Q_1 Q_0

    • Therefore, D1=P‾Q1+P‾Q0+Q1Q0D_1 = \overline{P} Q_1 + \overline{P} Q_0 + Q_1 Q_0

  2. For flip-flop D0=Q0+D_0 = Q_0^+:

    • Minterms where $Q_0^+ = 1$: $m(0, 2, 3, 6)$

    • Grouping on a 3-variable K-map:

      • Group 1 (m0,m2m_0, m_2): P‾ Q0‾\overline{P}\,\overline{Q_0}

      • Group 2 (m2,m3m_2, m_3): P‾Q1\overline{P} Q_1

      • Group 3 (m2,m6m_2, m_6): Q1Q0‾Q_1 \overline{Q_0}

    • Therefore, D0=P‾ Q0‾+P‾Q1+Q1Q0‾D_0 = \overline{P}\,\overline{Q_0} + \overline{P} Q_1 + Q_1 \overline{Q_0}

Hence, option (B) is the correct choice.

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This Combinational and Sequential Circuits previous year question is Q37 of the GATE CSE 2026 Set 1 paper. Find more GATE CSE PYQs on Combinational and Sequential Circuits in Digital Logic, or browse all GATE CSE PYQs.

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Combinational and Sequential Circuits has 32 GATE CSE PYQs across 22 papers from 2011 to 2026. 14 of them are 2-mark MCQs like this one, and it is the only one in GATE CSE 2026 Set 1.

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GateAI solution cardGATE CSE 2026 Set 1 · Q37 · MCQ

Consider a 2-bit saturating up/down counter that performs the saturating up count when the input P is 0, and the saturating down count when P is 1. The Next State table of the counter is as shown. The counter is built as a synchronous sequential circuit using D flip-flops. Which one of the following options corresponds to the expressions for the inputs of the D flip-flops, D1 and D0?

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Independent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.