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Combinational and Sequential Circuits

GATE CSE 2024 Set 1 · Q64

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Consider a digital logic circuit consisting of three 2-to-1 multiplexers M1, M2, and M3 as shown below. X1 and X2 are inputs of M1. X3 and X4 are inputs of M2. A, B, and C are select lines of M1, M2, and M3, respectively. For an instance of inputs X1=1X1=1, X2=1X2=1, X3=0X3=0, and X4=0X4=0, the number of combinations of A, B, C that give the output Y=1Y=1 is _______

GATE CSE 2024 Set 1 Q64 diagram

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Official answer: 4

Combinational and Sequential Circuits

Given the inputs to the multiplexers:

  • For multiplexer M1 with select line AA and inputs X1=1,X2=1X1 = 1, X2 = 1:

    Q1=A‾⋅X1+A⋅X2=A‾(1)+A(1)=1Q1 = \overline{A} \cdot X1 + A \cdot X2 = \overline{A}(1) + A(1) = 1

    Q1=1Q1 = 1 irrespective of the value of AA.

  • For multiplexer M2 with select line BB and inputs X3=0,X4=0X3 = 0, X4 = 0:

    Q2=B‾⋅X3+B⋅X4=B‾(0)+B(0)=0Q2 = \overline{B} \cdot X3 + B \cdot X4 = \overline{B}(0) + B(0) = 0

    Q2=0Q2 = 0 irrespective of the value of BB.

  • Multiplexer M3 has inputs Q1Q1 (at line 0) and Q2Q2 (at line 1), with select line CC:

    Y=C‾⋅Q1+C⋅Q2=C‾(1)+C(0)=C‾Y = \overline{C} \cdot Q1 + C \cdot Q2 = \overline{C}(1) + C(0) = \overline{C}

For the output Y=1Y = 1, we must have:

C‾=1  ⟹  C=0\overline{C} = 1 \implies C = 0

Since Y=1Y = 1 only requires C=0C = 0:

  • AA can be 00 or 11 (2 possibilities)

  • BB can be 00 or 11 (2 possibilities)

  • CC must be 00 (1 possibility)

Thus, the total number of combinations of (A,B,C)(A, B, C) is:

2×2×1=42 \times 2 \times 1 = 4

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This Combinational and Sequential Circuits previous year question is Q64 of the GATE CSE 2024 Set 1 paper. Find more GATE CSE PYQs on Combinational and Sequential Circuits in Digital Logic, or browse all GATE CSE PYQs.

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Combinational and Sequential Circuits has 32 GATE CSE PYQs across 22 papers from 2011 to 2026. 4 of them are 2-mark NAT questions like this one, and it is the only one in GATE CSE 2024 Set 1.

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GateAI solution cardGATE CSE 2024 Set 1 · Q64 · NAT

Consider a digital logic circuit consisting of three 2-to-1 multiplexers M1, M2, and M3 as shown below. X1 and X2 are inputs of M1. X3 and X4 are inputs of M2. A, B, and C are select lines of M1, M2, and M3, respectively. For an instance of inputs X1=1, X2=1, X3=0, and X4=0, the number of combinations of A, B, C that give the output Y=1 is …

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