Let R1 and R2 be two 4-bit registers that store numbers in 2's complement form. For the operation R1+R2, which one of the following values of R1 and R2 gives an arithmetic overflow?
Topic-wise GATE CS PYQs with verified steps
GATE CSE 2022 · Q18
Time
Select one answerSingle correct
Solution
Official answer: B) R1 = 1100 and R2 = 1010
Number Representation and ArithmeticIn 4-bit 2's complement representation, the representable range of signed integers is:
An arithmetic overflow occurs when adding two numbers of the same sign produces a result outside this range (i.e., adding two negative numbers yields a positive result, or adding two positive numbers yields a negative result).
Let us evaluate each option:
Option (A):
Since , no overflow occurs.
Option (B):
Since , the result is outside the representable range.
In 4-bit binary addition: . Taking the lower 4 bits gives , which has the wrong sign. The carry into MSB is and carry out is , giving overflow . Thus, overflow occurs.
Option (C):
(No overflow).
Option (D):
(No overflow).
Hence, (B) is the correct option.
Try the question first, then check your work.
Examiner trap
Find the range of 4-bit 2's complement numbers, , and check which sum falls outside this range.
This Number Representation and Arithmetic previous year question is Q18 of the GATE CSE 2022 paper. Find more GATE CSE PYQs on Number Representation and Arithmetic in Digital Logic, or browse all GATE CSE PYQs.
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Number Representation and Arithmetic has 33 GATE CSE PYQs across 20 papers from 2012 to 2026. 13 of them are 1-mark MCQs like this one, and GATE CSE 2022 has 2.
How GATE tests Number Representation and ArithmeticIndependent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.