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Boolean Algebra and Minimization

GATE CSE 2024 Set 1 · Q28

MSQ1 markMedium

Time

Consider the circuit shown below where the gates may have propagation delays. Assume that all signal transitions occur instantaneously and that wires have no delays. Which of the following statements about the circuit is/are CORRECT?

GATE CSE 2024 Set 1 Q28 diagram

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Solution

Step-by-step verified solution

Official answer: A) With no propagation delays, the output Y is always logic Zero; C) With propagation delays, the output Y can have a transient logic One after X transitions from logic Zero to logic One

Boolean Algebra and Minimization

The given circuit computes the Boolean function:

Y=X⋅X‾Y = X \cdot \overline{X}
  1. Ideal Case (No Propagation Delays):

    • In Boolean algebra, X⋅X‾=0X \cdot \overline{X} = 0 for all values of XX.

    • Hence, with no propagation delays, the output YY is always logic Zero.

    *(Statement A is correct, Statement B is incorrect)*

  2. Real Case (With Propagation Delays):

    • Let the NOT gate have a propagation delay of Δt>0\Delta t > 0.

    • Consider XX transitioning from logic Zero to logic One at t=0t = 0:

      • The direct input to the AND gate becomes 11 at t=0t = 0.

      • The output of the NOT gate was 11 (for X=0X = 0) and remains 11 for 0≤t<Δt0 \le t < \Delta t due to propagation delay.

      • During this time interval (0,Δt)(0, \Delta t), both inputs to the AND gate are 11.

      • Consequently, the output YY produces a transient high pulse (logic One) known as a static-0 hazard / glitch.

      *(Statement C is correct)*

    • Consider XX transitioning from logic One to logic Zero at t=0t = 0:

      • The direct input to the AND gate immediately drops to 00 at t=0t = 0.

      • The output of the NOT gate remains 00 until t=Δtt = \Delta t before changing to 11.

      • The inputs to the AND gate are (0,0)(0, 0) initially and then (0,1)(0, 1), so the output YY remains steady at logic Zero with no glitch.

      *(Statement D is incorrect)*

Therefore, the correct statements are A and C.

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This Boolean Algebra and Minimization previous year question is Q28 of the GATE CSE 2024 Set 1 paper. Find more GATE CSE PYQs on Boolean Algebra and Minimization in Digital Logic, or browse all GATE CSE PYQs.

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Boolean Algebra and Minimization in GATE CSE

Boolean Algebra and Minimization has 36 GATE CSE PYQs across 23 papers from 2011 to 2026. 5 of them are 1-mark MSQs like this one, and GATE CSE 2024 Set 1 has 2.

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GateAI solution cardGATE CSE 2024 Set 1 · Q28 · MSQ

Consider the circuit shown below where the gates may have propagation delays. Assume that all signal transitions occur instantaneously and that wires have no delays. Which of the following statements about the circuit is/are CORRECT?

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Independent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.