Consider a 5-stage pipelined processor with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Register Writeback (WB) stages. Which of the following statements about forwarding is/are CORRECT? A) In a pipelined execution, forwarding means the result from a source stage of an earlier instruction is passed on to the destination stage of a later instruction B) In forwarding, data from the output of the MEM stage can be passed on to the input of the EX stage of the next instruction C) Forwarding cannot prevent all pipeline stalls D) Forwarding does not require any extra hardware to retrieve the data from the pipeline stages

Official answer: A) In a pipelined execution, forwarding means the result from a source stage of an earlier instruction is passed on to the destination stage of a later instruction; B) In forwarding, data from the output of the MEM stage can be passed on to the input of the EX stage of the next instruction; C) Forwarding cannot prevent all pipeline stalls. Explanation: Evaluating each statement regarding operand forwarding (bypassing) in a 5-stage pipeline: - Statement (A): Forwarding routes an intermediate result from a pipeline register/stage of an earlier instruction directly to the input of a functional unit (destination stage) of a later instruction that needs it before it is written back to the register file. Hence, (A) is correct. - Statement (B): In a load-use situation or when memory output is required by a subsequent instruction's execution stage, data from the output of the MEM stage (such as the output of the MEM/WB register) can be forwarded to the input of the EX stage of the following instruction. Hence, (B) is correct. - Statement (C): Forwarding cannot eliminate all pipeline stalls. A classic example is a load-use data hazard where a `LOAD` instruction is immediately followed by an ALU instruction dependent on the loaded data; because the loaded data is only available at the end of the MEM stage, a 1-cycle stall is unavoidable even with forwarding. Hence, (C) is correct. - Statement (D): Forwarding requires extra hardware including multiplexers at the ALU inputs, comparator circuits (hazard detection/forwarding unit), and bypass datapath buses from pipeline registers back to earlier stages. Thus, (D) is incorrect. Therefore, statements (A), (B), and (C) are correct.

A) In a pipelined execution, forwarding means the result from a source stage of an earlier instruction is passed on to the destination stage of a later instruction

B) In forwarding, data from the output of the MEM stage can be passed on to the input of the EX stage of the next instruction

C) Forwarding cannot prevent all pipeline stalls

D) Forwarding does not require any extra hardware to retrieve the data from the pipeline stages

Computer Organization and Architecture · Instruction Pipelining

Official IIT answer key · IISc Bangalore · Audited Aug 2026

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GATE CSE 2024 Set 1 Q30 · MSQ · 1 mark

Consider a 5-stage pipelined processor with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Register Writeback (WB) stages. Which of the following statements about forwarding is/are CORRECT?

Select one or more options

Key concept

Instruction Pipelining

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How GATE tests Instruction Pipelining

Instruction pipelining and pipeline hazards are tested extensively with a heavy numerical skew (primarily 2-mark NATs). GATE focuses on evaluating effective CPI and speedup under realistic hazard scenarios (data, control, and structural), calculating clock cycle time from bottleneck stage delays and latch latencies, and analyzing cycle-by-cycle instruction progression with or without operand forwarding. Conceptual items frequently test dependency classifications (RAW, WAR, WAW) and the mechanics of operand bypassing.

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Independent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.

Computer Organization and Architecture · Instruction Pipelining

Official IIT answer key · IISc Bangalore · Audited Aug 2026

Take topic test

GATE CSE 2024 Set 1 Q30 · MSQ · 1 mark

Consider a 5-stage pipelined processor with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Register Writeback (WB) stages. Which of the following statements about forwarding is/are CORRECT?

Select one or more options

Key concept

Instruction Pipelining

Step-by-step verified solution

Examiner trap & misconception

Topic notes

How GATE tests Instruction Pipelining

Full Instruction Pipelining guide →

More on Instruction Pipelining

All 25 questions on Instruction Pipelining →

Independent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.

Consider a 5-stage pipelined processor with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Register Writeback (WB) stages. Which of the following statements about forwarding is/are CORRECT?

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Check you can still solve Instruction Pipelining under a clock

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Consider a 5-stage pipelined processor with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Register Writeback (WB) stages. Which of the following statements about forwarding is/are CORRECT?

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Consider a 5-stage pipelined processor with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Register Writeback (WB) stages. Which of the following statements about forwarding is/are CORRECT?

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Consider a 5-stage pipelined processor with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Register Writeback (WB) stages. Which of the following statements about forwarding is/are CORRECT?

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