Consider a 5-stage pipelined processor with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Register Writeback (WB) stages. Which of the following statements about forwarding is/are CORRECT?

Evaluating each statement regarding operand forwarding (bypassing) in a 5-stage pipeline:

• Statement (A): Forwarding routes an intermediate result from a pipeline register/stage of an earlier instruction directly to the input of a functional unit (destination stage) of a later instruction that needs it before it is written back to the register file. Hence, (A) is correct.

• Statement (B): In a load-use situation or when memory output is required by a subsequent instruction's execution stage, data from the output of the MEM stage (such as the output of the MEM/WB register) can be forwarded to the input of the EX stage of the following instruction. Hence, (B) is correct.

• Statement (C): Forwarding cannot eliminate all pipeline stalls. A classic example is a load-use data hazard where a LOAD instruction is immediately followed by an ALU instruction dependent on the loaded data; because the loaded data is only available at the end of the MEM stage, a 1-cycle stall is unavoidable even with forwarding. Hence, (C) is correct.

• Statement (D): Forwarding requires extra hardware including multiplexers at the ALU inputs, comparator circuits (hazard detection/forwarding unit), and bypass datapath buses from pipeline registers back to earlier stages. Thus, (D) is incorrect.

Therefore, statements (A), (B), and (C) are correct.