Consider the following logic circuit diagram. Which is/are the CORRECT option(s) for the output function F?
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GATE CSE 2025 Set 2 · Q31
Time

Select all that applyOne or more correct
Solution
Official answer: A) XY; B) X + Y + X Y; C) XY + X + X Y
Boolean Algebra and MinimizationFrom the given logic circuit, we trace the three inputs feeding into the final 3-input OR gate:
Top Gate (NAND gate): Inputs are and , so its output is:
Middle Gate (NOT gate): Input is , so its output is:
Bottom Gate (AND gate): Inputs are and (from the NOT gate applied to ), so its output is:
Combining these through the 3-input OR gate gives the unsimplified output function :
This directly matches Option (C).
Now, simplifying using De Morgan's Law and Boolean algebra:
This directly matches Option (B).
Further simplifying:
This matches Option (A).
Option (D) is .
Therefore, the correct options are A, B, and C.
Try the question first, then check your work.
Examiner trap
Write the Boolean expression at the output of each gate feeding the OR gate, and then simplify using De Morgan's laws and absorption laws.
This Boolean Algebra and Minimization previous year question is Q31 of the GATE CSE 2025 Set 2 paper. Find more GATE CSE PYQs on Boolean Algebra and Minimization in Digital Logic, or browse all GATE CSE PYQs.
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Boolean Algebra and Minimization has 36 GATE CSE PYQs across 23 papers from 2011 to 2026. 5 of them are 1-mark MSQs like this one, and GATE CSE 2025 Set 2 has 3.
How GATE tests Boolean Algebra and MinimizationIndependent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.