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Instruction Set and Addressing Modes

GATE CSE 2025 Set 2 · Q28

MSQ1 markEasy

Time

Which of the following is/are part of an Instruction Set Architecture of a processor?

Select all that applyOne or more correct

Pick every correct option

Solution

Step-by-step verified solution

Official answer: D) The total number of registers

Instruction Set and Addressing Modes

An Instruction Set Architecture (ISA) defines the programmer-visible interface of the processor, which includes:

  • The instruction set (operations, opcodes, formats)

  • Addressing modes and data types

  • The programmer-visible register file, including the total number of architectural registers

  • Memory addressing and byte ordering

In contrast, microarchitectural and hardware implementation details include:

  • Size of cache memory (Option A)

  • Processor clock frequency (Option B)

  • Number of cache memory levels (Option C)

These microarchitectural features are transparent to the ISA. Therefore, only D is part of the ISA.

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This Instruction Set and Addressing Modes previous year question is Q28 of the GATE CSE 2025 Set 2 paper. Find more GATE CSE PYQs on Instruction Set and Addressing Modes in Computer Organization and Architecture, or browse all GATE CSE PYQs.

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Instruction Set and Addressing Modes in GATE CSE

Instruction Set and Addressing Modes has 19 GATE CSE PYQs across 15 papers from 2011 to 2026. This is the only 1-mark MSQ among them, and it is the only one in GATE CSE 2025 Set 2.

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Which of the following is/are part of an Instruction Set Architecture of a processor?

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Independent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.