Computer Organization and Architecture · ALU Design
Official IIT answer key · IIT Guwahati · Audited Aug 2026
GATE CSE 2025 Set 2 Q32 · NAT · 1 mark
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Topic notes
Across GATE CS exams (2016–2025), questions on ALU design evaluate three foundational pillars: the timing analysis and gate-level complexity of hardware adders (such as Carry Lookahead Adders), arithmetic algorithms implementation (specifically Booth's algorithm operations), and the integration of the ALU within CPU datapaths (control sequencing and multiplexer-based operand routing). Questions range from 1-mark architectural reasoning items to 2-mark algorithmic/complexity computations.
Full ALU Design guide →The following two signed 2's complement numbers (multiplicand M and multiplier Q) are being multiplied using Booth's algorithm: M: 1100 1101 1110 1101 and Q: 1010 0100 1010 1010 The total number of addition and subtraction operations to be performed is … (Answer in integer)
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