An instruction pipeline has five stages, namely, instruction fetch (IF), instruction decode and register fetch (ID/RF), instruction execution (EX), memory access (MEM), and register writeback (WB) with stage latencies 1 ns, 2.2 ns, 2 ns, 1 ns, and 0.75 ns, respectively (ns stands for nanoseconds). To gain in terms of frequency, the designers have decided to split the ID/RF stage into three stages (ID, RF1, RF2) each of latency 2.2/3 ns. Also, the EX stage is split into two stages (EX1, EX2) each of latency 1 ns. The new design has a total of eight pipeline stages. A program has 20% branch instructions which execute in the EX stage and produce the next instruction pointer at the end of the EX stage in the old design and at the end of the EX2 stage in the new design. The IF stage stalls after fetching a branch instruction until the next instruction pointer is computed. All instructions other than the branch instruction have an average CPI of one in both the designs. The execution times of this program on the old and the new design are $P$ and $Q$ nanoseconds, respectively. The value of $P/Q$ is ___________.

Old Design (5 stages):

• Stages: IF (1 ns), ID/RF (2.2 ns), EX (2 ns), MEM (1 ns), WB (0.75 ns).

• Clock cycle time $T_{\text{old}} = \max(1, 2.2, 2, 1, 0.75) = 2.2\text{ ns}$.

• Branch penalty: Branch is fetched in Stage 1 (IF) and completes target computation at the end of Stage 3 (EX). Thus, the IF stage stalls for $3 - 1 = 2$ cycles per branch instruction.

• Average CPI for old design:

  $$\text{CPI}_{\text{old}} = 1 + 0.20 \times 2 = 1.4$$

• Execution time $P = N \times \text{CPI}_{\text{old}} \times T_{\text{old}} = N \times 1.4 \times 2.2 = 3.08 N\text{ ns}$.

New Design (8 stages):

• Stages: IF (1 ns), ID ($2.2/3\text{ ns} \approx 0.733\text{ ns}$), RF1 ($0.733\text{ ns}$), RF2 ($0.733\text{ ns}$), EX1 (1 ns), EX2 (1 ns), MEM (1 ns), WB (0.75 ns).

• Clock cycle time $T_{\text{new}} = \max(1, 0.733, 0.733, 0.733, 1, 1, 1, 0.75) = 1\text{ ns}$.

• Branch penalty: Branch completes target computation at the end of Stage 6 (EX2). Thus, the IF stage stalls for $6 - 1 = 5$ cycles per branch instruction.

• Average CPI for new design:

  $$\text{CPI}_{\text{new}} = 1 + 0.20 \times 5 = 2.0$$

• Execution time $Q = N \times \text{CPI}_{\text{new}} \times T_{\text{new}} = N \times 2.0 \times 1 = 2.0 N\text{ ns}$.

Ratio $P/Q$:

Thus, the value of $P/Q$ is 1.54 (accepted range: 1.50 to 1.60).