Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume that there are no stalls in the pipeline. The speed up achieved in this pipelined processor is ________.

Speedup ($S$) of the pipelined processor over the non-pipelined processor is defined as:

1. For the non-pipelined processor:

   • Frequency $f_{\text{non-pipe}} = 2.5\text{ GHz}$

   • $\text{CPI}_{\text{non-pipe}} = 4$

   • Average execution time per instruction:

     $$T_{\text{non-pipe}} = \frac{\text{CPI}_{\text{non-pipe}}}{f_{\text{non-pipe}}} = \frac{4}{2.5\text{ GHz}} = 1.6\text{ ns}$$

2. For the pipelined processor:

   • Frequency $f_{\text{pipe}} = 2\text{ GHz}$

   • With no stalls in the pipeline, ideal $\text{CPI}_{\text{pipe}} = 1$

   • Average execution time per instruction:

     $$T_{\text{pipe}} = \frac{\text{CPI}_{\text{pipe}}}{f_{\text{pipe}}} = \frac{1}{2\text{ GHz}} = 0.5\text{ ns}$$

3. Speedup:

   $$S = \frac{1.6\text{ ns}}{0.5\text{ ns}} = 3.2$$

Hence, the speedup achieved is 3.2 [20].