Computer Organization and Architecture · Instruction Pipelining
Official IIT answer key · IIT Kanpur · Audited Aug 2026
GATE CSE 2015 Set 1 Q38 · NAT · 2 marks
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Topic notes
Instruction pipelining and pipeline hazards are tested extensively with a heavy numerical skew (primarily 2-mark NATs). GATE focuses on evaluating effective CPI and speedup under realistic hazard scenarios (data, control, and structural), calculating clock cycle time from bottleneck stage delays and latch latencies, and analyzing cycle-by-cycle instruction progression with or without operand forwarding. Conceptual items frequently test dependency classifications (RAW, WAR, WAW) and the mechanics of operand bypassing.
Full Instruction Pipelining guide →Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume that there are no stalls in the pipeline. The speed up achieved in this pipelined processor is …
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