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Cache Memory and Hierarchy

GATE CSE 2022 · Q40

MCQ2 marksMedium

Time

Consider a digital display system (DDS) shown in the figure that displays the contents of register X. A 16-bit code word is used to load a word in X, either from S or from R. S is a 1024-word memory segment and R is a 32-word register file. Based on the value of mode bit M, T selects an input word to load in X. P and Q interface with the corresponding bits in the code word to choose the addressed word. Which one of the following represents the functionality of P, Q, and T?

GATE CSE 2022 Q40 diagram

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Solution

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Official answer: C) P is 10:210 decoder; Q is 5:25 decoder; T is 2:1 multiplexer

Cache Memory and Hierarchy

To determine the functions of components P, Q, and T:

  1. Component P (Addressing Memory S):

    • Memory segment SS has 1024=2101024 = 2^{10} words.

    • To select one specific word among 10241024 locations, a 10-bit address is required.

    • An address decoder converts nn address lines to 2n2^n unique select lines.

    • Therefore, PP is a 10:21010:2^{10} (or 10:102410:1024) decoder.

  2. Component Q (Addressing Register File R):

    • Register file RR contains 32=2532 = 2^5 words.

    • To select one of the 3232 registers, a 5-bit address is needed.

    • Therefore, QQ is a 5:255:2^5 (or 5:325:32) decoder.

  3. Component T (Selecting between S and R):

    • TT receives two word inputs (one from SS and one from RR) and selects one to load into register XX based on the 1-bit mode control signal MM.

    • A component that selects one of two data inputs based on a control/select line is a 2:12:1 multiplexer (MUX).

Notice that the total code word size is 1 (for M)+10 (for S)+5 (for R)=16 bits1\text{ (for } M) + 10\text{ (for } S\text{)} + 5\text{ (for } R\text{)} = 16\text{ bits}, which matches the prompt.

Hence, P is a 10:21010:2^{10} decoder; Q is a 5:255:2^5 decoder; T is a 2:12:1 multiplexer, which corresponds to option (C).

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This Cache Memory and Hierarchy previous year question is Q40 of the GATE CSE 2022 paper. Find more GATE CSE PYQs on Cache Memory and Hierarchy in Computer Organization and Architecture, or browse all GATE CSE PYQs.

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Cache Memory and Hierarchy in GATE CSE

Cache Memory and Hierarchy has 47 GATE CSE PYQs across 23 papers from 2011 to 2026. 16 of them are 2-mark MCQs like this one, and GATE CSE 2022 has 4.

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GateAI solution cardGATE CSE 2022 · Q40 · MCQ

Consider a digital display system (DDS) shown in the figure that displays the contents of register X. A 16-bit code word is used to load a word in X, either from S or from R. S is a 1024-word memory segment and R is a 32-word register file. Based on the value of mode bit M, T selects an input word to load in X. P and Q interface with the corresponding bits in the code word to choose the addressed word. Which one of the following represents the functionality of P, Q, and T?

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Independent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.