To determine the functions of components P, Q, and T:
Component P (Addressing Memory S):
Memory segment S has 1024=210 words.
To select one specific word among 1024 locations, a 10-bit address is required.
An address decoder converts n address lines to 2n unique select lines.
Therefore, P is a 10:210 (or 10:1024) decoder.
Component Q (Addressing Register File R):
Register file R contains 32=25 words.
To select one of the 32 registers, a 5-bit address is needed.
Therefore, Q is a 5:25 (or 5:32) decoder.
Component T (Selecting between S and R):
T receives two word inputs (one from S and one from R) and selects one to load into register X based on the 1-bit mode control signal M.
A component that selects one of two data inputs based on a control/select line is a 2:1 multiplexer (MUX).
Notice that the total code word size is 1 (for M)+10 (for S)+5 (for R)=16 bits, which matches the prompt.
Hence, P is a 10:210 decoder; Q is a 5:25 decoder; T is a 2:1 multiplexer, which corresponds to option (C).