What are common examiner traps in I/O Interface, Interrupts and DMA?

Confusing Daisy Chaining with Polling: Assuming Daisy Chaining requires the CPU to poll devices sequentially, whereas Daisy Chaining is a purely hardware-propagated signal (INTA). Unit conversion errors: Missing bytes-to-bits conversion (e.g., multiplying 8 bytes/cycle by 8 to get 64 bits/cycle) when calculating data transfer rates in bits per second. Ignoring register capacity limits: Forgetting that a k-bit counter can only transfer at most 2k units per DMA grant, requiring ceiling division for total bus acquisitions. Interrupt execution boundary confusion: Thinking the CPU handles an interrupt immediately in the middle of executing an instruction rather than completing the current instruction first. Bus Master concurrency: Assuming DMA controller and CPU can both act as active bus masters simultaneously (violates shared bus arbitration). Unit conversion errors between seconds (s), milliseconds (ms), and microseconds ( s). Forgetting to include the additional data processing time when a polling check detects an active event. Incorrectly calculating the number of polling cycles per unit time (e.g., miscalculating 1 s10 ms = 100 polls). Confusing total execution time per interrupt with interrupt latency or forgetting ISR overhead.

I/O Interface, Interrupts and DMA

13 Qs · since 2011 · 16 marks · 0.6 marks/paperStandard yield

Take topic test

GATE tests I/O interface (Interrupt and DMA) across two main facets: conceptual understanding of I/O transfer mechanisms (Programmed I/O, Interrupt-driven I/O, and DMA modes) along… Guide

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GATE CSE 2026 Set 2Q18MCQ1 markEasyConsider the following two statements about interrupt handling mechanisms in a CPU. S1: In non-vectored interrupt mechanism, it usually takes more time to start the Interrupt Service Routine (ISR) when compared to that in a vectored interrupt mechanism. S2: In daisy-chain interrupt mechanism, the CPU polls all the…
GATE CSE 2025 Set 1Q11MCQ1 markEasySuppose a program is running on a non-pipelined single processor computer system. The computer is connected to an external device that can interrupt the processor asynchronously. The processor needs to execute the interrupt service routine (ISR) to serve this interrupt. The following steps (not necessarily in order)…
GATE CSE 2024 Set 1Q15MCQ1 markEasyWhich one of the following statements is FALSE?
GATE CSE 2024 Set 2Q11MCQ1 markEasyConsider a computer with a 4 MHz processor. Its DMA controller can transfer 8 bytes in 1 cycle from a device to main memory through cycle stealing at regular intervals. Which one of the following is the data transfer rate ( $\textit{in bits per second}$ ) of the DMA controller if 1% of the processor cycles are used for…
GATE CSE 2023Q34NAT1 markEasyA keyboard connected to a computer is used at a rate of 1 keystroke per second. The computer system polls the keyboard every 10 ms (milli seconds) to check for a keystroke and consumes 100 $\mu$ s (micro seconds) for each poll. If it is determined after polling that a key has been pressed, the system consumes an…
GATE CSE 2022Q17MCQ1 markEasyWhich one of the following facilitates transfer of bulk data from hard disk to main memory with the highest throughput?
GATE CSE 2021 Set 2Q20NAT1 markEasyConsider a computer system with DMA support. The DMA module is transferring one 8-bit character in one CPU cycle from a device to memory through cycle stealing at regular intervals. Consider a 2 MHz processor. If 0.5% processor cycles are used for DMA, the data transfer rate of the device is ________ bits per second.
GATE CSE 2020Q3MCQ1 markEasyConsider the following statements. I. Daisy chaining is used to assign priorities in attending interrupts. II. When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt. III. In polling, the CPU periodically checks the status bits to know if any device needs its attention.…
GATE CSE 2018Q9MCQ1 markEasyThe following are some events that occur after a device controller issues an interrupt while process $L$ is under execution. (P) The processor pushes the process status of $L$ onto the control stack. (Q) The processor finishes the execution of the current instruction. (R) The processor executes the interrupt…
GATE CSE 2016 Set 1Q31NAT2 marksMediumThe size of the data count register of a DMA controller is 16 bits. The processor needs to transfer a file of 29,154 kilobytes from disk to main memory. The memory is byte addressable. The minimum number of times the DMA controller needs to get the control of the system bus from the processor to transfer the file from…
GATE CSE 2013Q28MCQ2 marksEasyConsider the following sequence of micro-operations. MBR $\leftarrow$ PC MAR $\leftarrow$ X PC $\leftarrow$ Y Memory $\leftarrow$ MBR Which one of the following is a possible operation performed by this sequence?
GATE CSE 2011Q11MCQ1 markEasyA computer handles several interrupt sources of which the following are relevant for this question. • Interrupt from CPU temperature sensor (raises interrupt if CPU temperature is too high) • Interrupt from Mouse (raises interrupt if the mouse is moved or a button is pressed) • Interrupt from Keyboard (raises…
GATE CSE 2011Q28MCQ2 marksMediumOn a non-pipelined sequential processor, a program segment, which is a part of the interrupt service routine, is given to transfer 500 bytes from an I/O device to memory. Initialize the address register Initialize the count to 500 LOOP: Load a byte from device Store in memory at address given by address register Increment the address register Decrement the count If count != 0 go to LOOP…

Topic guide

What does GATE test in I/O Interface, Interrupts and DMA?

GATE tests I/O interface (Interrupt and DMA) across two main facets: conceptual understanding of I/O transfer mechanisms (Programmed I/O, Interrupt-driven I/O, and DMA modes) alongside quantitative calculations on DMA bandwidth, cycle stealing, and register limits. Conceptual questions regularly assess interrupt lifecycle events, priority resolution (Daisy chaining vs Polling), and vectored vs non-vectored interrupt handling. Numerical questions focus on DMA throughput given processor clock frequency and stolen cycle percentages, as well as transfer chunking governed by DMA data counter bit-widths.

Core concepts

Interrupt lifecycle: instruction completion boundary, saving PSW/PC to stack, vector fetch, ISR execution, stack restoration
Interrupt classification & priority: Non-maskable/hardware emergencies (CPU temperature, power failure) vs standard I/O devices
Vectored vs Non-vectored interrupts: Hardware-supplied vector address vs common vector requiring software polling
Priority resolution mechanisms: Daisy chaining (hardware serial grant signal) vs Software polling (CPU reads device status registers)
DMA Controller architecture: Address register, Word/Byte count register, Control status register
DMA Modes: Burst mode (block transfer, bus locked) vs Cycle stealing mode (interleaved single-word transfers)
Bus Mastership: Mutual exclusion of CPU and DMA controller on the system bus
Throughput and CPU utilization comparison: Programmed I/O (worst CPU utilization) < Interrupt-driven < DMA (highest bulk throughput)
Programmed I/O / Polling mechanism and polling frequency
Interrupt-driven I/O and Interrupt Service Routine (ISR) overhead
CPU utilization and time fraction calculation for I/O operations
Time unit normalization (seconds, milliseconds, microseconds)

Recurring question patterns

DMA Cycle-Stealing Bandwidth Calculation
common · mixed · 1 marks · 2024, 2021
Given CPU clock frequency, percentage of cycles stolen by the DMA controller, and bytes/characters transferred per stolen cycle, calculate the effective data transfer rate in bits per second (bps) or bytes per second.
DMA Transfer Count / Bus Acquisition Limit
occasional · NAT · 2 marks · 2016
Given a DMA controller's data count register width (e.g., 16 bits) and a large file size to transfer, calculate the minimum number of distinct DMA bus acquisitions (transfers) required by taking the ceiling division of the file size over the maximum transfer capacity per operation ( $2^n$ bytes).
Interrupt Service Lifecycle and Micro-operations
common · MCQ · 1 marks · 2018, 2013
Identify the precise chronological ordering of hardware and software steps during interrupt handling (finish current instruction -> save status/PC -> load vector -> execute ISR -> restore status) or identify register transfer micro-operations representing interrupt initiation.
Comparative Assessment of I/O Schemes and Priority Resolution
common · MCQ · 1 marks · 2026, 2024, 2022, 2020
Evaluate multi-statement truth values comparing Programmed I/O, Interrupt-Driven I/O, and DMA transfer modes (burst vs cycle stealing), bus master arbitration rules, hardware priority (Daisy chaining) vs software polling, or hardware priority ordering (e.g., thermal sensors vs peripherals).
Execution Time & Speedup: Programmed/Interrupt ISR vs DMA
rare · MCQ · 2 marks · 2011
Compute the clock cycle overhead of an instruction-driven ISR transfer loop versus DMA initialization and block transfer cycles to find the resulting speedup.
Polling vs Interrupt Overhead Comparison
rare · NAT · 1 marks · 2023
Given an I/O device arrival rate (e.g., keystrokes/sec), polling frequency, polling check time, and processing/ISR execution times, calculate the total CPU time or fraction spent under both polling and interrupt-driven modes, then determine their ratio or difference.

Formulas GATE uses

DMA Transfer Rate in Cycle-Stealing Mode

\text{Data Transfer Rate (bps)} = f_{\text{CPU}} \times \left(\frac{P_{\text{stolen}}}{100}\right) \times \text{Bits per Cycle}

Used to determine device transfer rate when DMA steals a fixed percentage $P_{\text{stolen}}$ of processor cycles running at frequency $f_{\text{CPU}}$ .

Maximum DMA Block Size per Bus Request

\text{Max Block Size} = 2^{k} \times \text{Addressable Unit Size}

Used when finding the maximum chunk a DMA controller can transfer in one operation given a $k$ -bit count register.

Number of DMA Bus Grants Required

\text{Number of Transfers} = \left\lceil \frac{\text{Total File Size}}{\text{Max Block Size per Transfer}} \right\rceil

Used to find the minimum times DMA requests the system bus to transfer a file larger than its register capacity.

Speedup of DMA over Programmed/ISR I/O

\text{Speedup} = \frac{\text{Cycles}_{\text{ISR}}}{\text{Cycles}_{\text{DMA}}} = \frac{\text{Overhead}_{\text{ISR}} + (N \times \text{Cycles per loop iteration})}{\text{Overhead}_{\text{DMA}} + (N \times \text{Cycles per transfer})}

Used when comparing total cycle execution time of an interrupt routine vs DMA hardware transfer for $N$ units of data.

Polling Overhead per Second

T_1 = \left(\frac{1\text{ s}}{\text{Polling Interval}} \times t_{\text{poll}}\right) + (\text{Event Rate} \times t_{\text{process}})

Used to compute total CPU time fraction spent checking device status and processing detected I/O events in a polling system.

Interrupt Service Overhead per Second

T_2 = \text{Event Rate} \times t_{\text{ISR}}

Used to compute total CPU time fraction consumed by servicing device interrupts and processing data.

Overhead Ratio

\text{Ratio} = \frac{T_1}{T_2}

Used to compare the relative CPU time spent between polling and interrupt-driven implementations.

Examiner traps in I/O Interface, Interrupts and DMA

Confusing Daisy Chaining with Polling: Assuming Daisy Chaining requires the CPU to poll devices sequentially, whereas Daisy Chaining is a purely hardware-propagated signal (INTA).
Unit conversion errors: Missing bytes-to-bits conversion (e.g., multiplying 8 bytes/cycle by 8 to get 64 bits/cycle) when calculating data transfer rates in bits per second.
Ignoring register capacity limits: Forgetting that a k-bit counter can only transfer at most 2k units per DMA grant, requiring ceiling division for total bus acquisitions.
Interrupt execution boundary confusion: Thinking the CPU handles an interrupt immediately in the middle of executing an instruction rather than completing the current instruction first.
Bus Master concurrency: Assuming DMA controller and CPU can both act as active bus masters simultaneously (violates shared bus arbitration).
Unit conversion errors between seconds (s), milliseconds (ms), and microseconds ( s).
Forgetting to include the additional data processing time when a polling check detects an active event.
Incorrectly calculating the number of polling cycles per unit time (e.g., miscalculating 1 s10 ms = 100 polls).
Confusing total execution time per interrupt with interrupt latency or forgetting ISR overhead.

How questions are asked

Multi-statement true/false evaluation (Statements I to IV or S1/S2)
Direct chronological sequencing of interrupt handling events
NAT bandwidth calculation from CPU clock rate, stolen cycle fraction, and word size
NAT bus-request count calculation using register bit-width and transfer size
Micro-operation identification for interrupt initiation sequence
Comparative speedup calculation between ISR loop and DMA transfer
Calculate ratio of CPU time spent in polling versus interrupt-driven I/O (NAT)
Determine percentage CPU overhead consumed by an I/O interface

Paper trends

Shift from multi-step cycle-by-cycle speedup problems (2011) towards concise 1-mark numerical calculations on cycle-stealing transfer rate and statement-verification MCQs.
2024, 2021, 2011
Consistent recurrence of conceptual comparison items testing the precise distinction between Daisy chaining (hardware vector propagation) and software polling, as well as vectored vs non-vectored ISR startup latency.
2026, 2024, 2020
High prevalence of 1-mark Easy/Medium items directly testing standard textbook properties (bus master exclusivity, relative throughput, interrupt priority).
2026, 2024, 2022, 2020, 2018
Quantitative evaluation of I/O interface mechanisms has been introduced via NAT format, shifting focus from purely qualitative device interface definitions to numerical CPU time fraction calculations.
2023

Difficulty notes

Easy items (1 mark) test fundamental definitions: sequence of interrupt events, highest priority device identification, bus master exclusivity, or direct cycle-stealing rate calculations. Medium items (2 marks) involve multi-step arithmetic such as calculating required bus acquisitions using ceiling division on register capacities, or computing speedup ratios between assembly ISR loops and DMA hardware overheads.

I/O Interface, Interrupts and DMA

13 Qs · since 2011 · 16 marks · 0.6 marks/paperStandard yield

Take topic test

GATE tests I/O interface (Interrupt and DMA) across two main facets: conceptual understanding of I/O transfer mechanisms (Programmed I/O, Interrupt-driven I/O, and DMA modes) along… Guide

Type

Topic guide

What does GATE test in I/O Interface, Interrupts and DMA?

Core concepts

Interrupt lifecycle: instruction completion boundary, saving PSW/PC to stack, vector fetch, ISR execution, stack restoration
Interrupt classification & priority: Non-maskable/hardware emergencies (CPU temperature, power failure) vs standard I/O devices
Vectored vs Non-vectored interrupts: Hardware-supplied vector address vs common vector requiring software polling
Priority resolution mechanisms: Daisy chaining (hardware serial grant signal) vs Software polling (CPU reads device status registers)
DMA Controller architecture: Address register, Word/Byte count register, Control status register
DMA Modes: Burst mode (block transfer, bus locked) vs Cycle stealing mode (interleaved single-word transfers)
Bus Mastership: Mutual exclusion of CPU and DMA controller on the system bus
Throughput and CPU utilization comparison: Programmed I/O (worst CPU utilization) < Interrupt-driven < DMA (highest bulk throughput)
Programmed I/O / Polling mechanism and polling frequency
Interrupt-driven I/O and Interrupt Service Routine (ISR) overhead
CPU utilization and time fraction calculation for I/O operations
Time unit normalization (seconds, milliseconds, microseconds)

Recurring question patterns

DMA Cycle-Stealing Bandwidth Calculation
common · mixed · 1 marks · 2024, 2021
Given CPU clock frequency, percentage of cycles stolen by the DMA controller, and bytes/characters transferred per stolen cycle, calculate the effective data transfer rate in bits per second (bps) or bytes per second.
DMA Transfer Count / Bus Acquisition Limit
occasional · NAT · 2 marks · 2016
Given a DMA controller's data count register width (e.g., 16 bits) and a large file size to transfer, calculate the minimum number of distinct DMA bus acquisitions (transfers) required by taking the ceiling division of the file size over the maximum transfer capacity per operation ( $2^n$ bytes).
Interrupt Service Lifecycle and Micro-operations
common · MCQ · 1 marks · 2018, 2013
Identify the precise chronological ordering of hardware and software steps during interrupt handling (finish current instruction -> save status/PC -> load vector -> execute ISR -> restore status) or identify register transfer micro-operations representing interrupt initiation.
Comparative Assessment of I/O Schemes and Priority Resolution
common · MCQ · 1 marks · 2026, 2024, 2022, 2020
Evaluate multi-statement truth values comparing Programmed I/O, Interrupt-Driven I/O, and DMA transfer modes (burst vs cycle stealing), bus master arbitration rules, hardware priority (Daisy chaining) vs software polling, or hardware priority ordering (e.g., thermal sensors vs peripherals).
Execution Time & Speedup: Programmed/Interrupt ISR vs DMA
rare · MCQ · 2 marks · 2011
Compute the clock cycle overhead of an instruction-driven ISR transfer loop versus DMA initialization and block transfer cycles to find the resulting speedup.
Polling vs Interrupt Overhead Comparison
rare · NAT · 1 marks · 2023
Given an I/O device arrival rate (e.g., keystrokes/sec), polling frequency, polling check time, and processing/ISR execution times, calculate the total CPU time or fraction spent under both polling and interrupt-driven modes, then determine their ratio or difference.

Formulas GATE uses

DMA Transfer Rate in Cycle-Stealing Mode

\text{Data Transfer Rate (bps)} = f_{\text{CPU}} \times \left(\frac{P_{\text{stolen}}}{100}\right) \times \text{Bits per Cycle}

Used to determine device transfer rate when DMA steals a fixed percentage $P_{\text{stolen}}$ of processor cycles running at frequency $f_{\text{CPU}}$ .

Maximum DMA Block Size per Bus Request

\text{Max Block Size} = 2^{k} \times \text{Addressable Unit Size}

Used when finding the maximum chunk a DMA controller can transfer in one operation given a $k$ -bit count register.

Number of DMA Bus Grants Required

\text{Number of Transfers} = \left\lceil \frac{\text{Total File Size}}{\text{Max Block Size per Transfer}} \right\rceil

Used to find the minimum times DMA requests the system bus to transfer a file larger than its register capacity.

Speedup of DMA over Programmed/ISR I/O

\text{Speedup} = \frac{\text{Cycles}_{\text{ISR}}}{\text{Cycles}_{\text{DMA}}} = \frac{\text{Overhead}_{\text{ISR}} + (N \times \text{Cycles per loop iteration})}{\text{Overhead}_{\text{DMA}} + (N \times \text{Cycles per transfer})}

Used when comparing total cycle execution time of an interrupt routine vs DMA hardware transfer for $N$ units of data.

Polling Overhead per Second

T_1 = \left(\frac{1\text{ s}}{\text{Polling Interval}} \times t_{\text{poll}}\right) + (\text{Event Rate} \times t_{\text{process}})

Used to compute total CPU time fraction spent checking device status and processing detected I/O events in a polling system.

Interrupt Service Overhead per Second

T_2 = \text{Event Rate} \times t_{\text{ISR}}

Used to compute total CPU time fraction consumed by servicing device interrupts and processing data.

Overhead Ratio

\text{Ratio} = \frac{T_1}{T_2}

Used to compare the relative CPU time spent between polling and interrupt-driven implementations.

Examiner traps in I/O Interface, Interrupts and DMA

Confusing Daisy Chaining with Polling: Assuming Daisy Chaining requires the CPU to poll devices sequentially, whereas Daisy Chaining is a purely hardware-propagated signal (INTA).
Unit conversion errors: Missing bytes-to-bits conversion (e.g., multiplying 8 bytes/cycle by 8 to get 64 bits/cycle) when calculating data transfer rates in bits per second.
Ignoring register capacity limits: Forgetting that a k-bit counter can only transfer at most 2k units per DMA grant, requiring ceiling division for total bus acquisitions.
Interrupt execution boundary confusion: Thinking the CPU handles an interrupt immediately in the middle of executing an instruction rather than completing the current instruction first.
Bus Master concurrency: Assuming DMA controller and CPU can both act as active bus masters simultaneously (violates shared bus arbitration).
Unit conversion errors between seconds (s), milliseconds (ms), and microseconds ( s).
Forgetting to include the additional data processing time when a polling check detects an active event.
Incorrectly calculating the number of polling cycles per unit time (e.g., miscalculating 1 s10 ms = 100 polls).
Confusing total execution time per interrupt with interrupt latency or forgetting ISR overhead.

How questions are asked

Multi-statement true/false evaluation (Statements I to IV or S1/S2)
Direct chronological sequencing of interrupt handling events
NAT bandwidth calculation from CPU clock rate, stolen cycle fraction, and word size
NAT bus-request count calculation using register bit-width and transfer size
Micro-operation identification for interrupt initiation sequence
Comparative speedup calculation between ISR loop and DMA transfer
Calculate ratio of CPU time spent in polling versus interrupt-driven I/O (NAT)
Determine percentage CPU overhead consumed by an I/O interface

Paper trends

Shift from multi-step cycle-by-cycle speedup problems (2011) towards concise 1-mark numerical calculations on cycle-stealing transfer rate and statement-verification MCQs.
2024, 2021, 2011
Consistent recurrence of conceptual comparison items testing the precise distinction between Daisy chaining (hardware vector propagation) and software polling, as well as vectored vs non-vectored ISR startup latency.
2026, 2024, 2020
High prevalence of 1-mark Easy/Medium items directly testing standard textbook properties (bus master exclusivity, relative throughput, interrupt priority).
2026, 2024, 2022, 2020, 2018
Quantitative evaluation of I/O interface mechanisms has been introduced via NAT format, shifting focus from purely qualitative device interface definitions to numerical CPU time fraction calculations.
2023