What are common examiner traps in Instruction Pipelining?

Forgetting latch/register delay when computing clock period after stage splitting. Applying ideal formula (k+n-1) when dependencies or multi-cycle stages introduce stalls. Assuming forwarding eliminates all stalls (forgetting the unavoidable 1-cycle stall in load-use data hazards). Confusing WAR (anti-dependence) and WAW (output dependence) with RAW (true dependence). Miscalculating branch penalty: forgetting that branch outcome resolution at stage M incurs (M - 1) stall cycles for instruction fetch. In multi-cycle EX stage stalls, calculating stalls as k instead of (k - 1) per instruction. Summing up the individual stage delays for every instruction rather than using the bottleneck stage duration (ti) as the clock period. Off-by-one errors in cycle count (e.g., using k n or k + n instead of k + n - 1). Forgetting to convert time units (e.g., ns to cycles or vice versa). Omitting the buffer delay when calculating the pipeline cycle time (tcycle = (ti) instead of (ti) + tbuffer). Forgetting to update the number of pipeline stages k after splitting a bottleneck stage (e.g., failing to increment k from 5 to 6). Using asymptotic speedup (tcycle1 / tcycle2) instead of computing the finite instruction count execution time with (k + n - 1). Rounding speedup prematurely during intermediate steps rather than rounding to two decimal places at the final answer.

Instruction Pipelining

25 Qs · since 2011 · 44 marks · 1.8 marks/paperMedium yield

Take topic test

Instruction pipelining and pipeline hazards are tested extensively with a heavy numerical skew (primarily 2-mark NATs). GATE focuses on evaluating effective CPI and speedup under r… Guide

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GATE CSE 2026 Set 1Q16MCQ1 markEasyWhich one of the following dependencies among the register operands of different instructions can cause a data hazard in a pipelined processor?
GATE CSE 2026 Set 1Q60NAT2 marksMediumDiagramThe EX stage of a pipelined processor performs the memory read operations for LOAD instructions, and the operations for the arithmetic and logic instructions. Let $t_{EX}$ denote the time taken by the EX stage to perform the operation for an instruction. For each instruction type, the values of $t_{EX}$ and $M$ …
GATE CSE 2026 Set 2Q57NAT2 marksMediumA non-pipelined instruction execution unit that operates at 1.6 GHz clock takes an average of 5 clock cycles to complete the execution of an instruction. To improve the performance, the system was pipelined with a goal of achieving an average throughput of one instruction per clock cycle. However, it could operate…
GATE CSE 2025 Set 2Q56NAT2 marksMediumA 5-stage instruction pipeline has stage delays of 180, 250, 150, 170, and 250, respectively, in nanoseconds. The delay of an inter-stage latch is 10 nanoseconds. Assume that there are no pipeline stalls due to branches and other hazards. The time taken to process 1000 instructions in microseconds is _________ .…
GATE CSE 2024 Set 1Q30MSQ1 markMediumConsider a 5-stage pipelined processor with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Register Writeback (WB) stages. Which of the following statements about forwarding is/are CORRECT?
GATE CSE 2024 Set 2Q31MSQ1 markEasyAn instruction format has the following structure: Instruction Number: Opcode destination reg, source reg-1, source reg-2 Consider the following sequence of instructions to be executed in a pipelined processor: I1: DIV R3, R1, R2I2: SUB R5, R3, R4I3: ADD R3, R5, R6I4: MUL R7, R3, R8…
GATE CSE 2024 Set 2Q58NAT2 marksMediumA non-pipelined instruction execution unit operating at 2 GHz takes an average of 6 cycles to execute an instruction of a program P. The unit is then redesigned to operate on a 5-stage pipeline at 2 GHz. Assume that the ideal throughput of the pipelined unit is 1 instruction per cycle. In the execution of program P,…
GATE CSE 2023Q33NAT1 markEasyConsider a 3-stage pipelined processor having a delay of 10 ns (nanoseconds), 20 ns, and 14 ns, for the first, second, and the third stages, respectively. Assume that there is no other delay and the processor does not suffer from any pipeline hazards. Also assume that one instruction is fetched every cycle. The total…
GATE CSE 2022Q61NAT2 marksMediumA processor $X_1$ operating at 2 GHz has a standard 5-stage RISC instruction pipeline having a base CPI (cycles per instruction) of one without any pipeline hazards. For a given program P that has 30% branch instructions, control hazards incur 2 cycles stall for every branch. A new version of the processor $X_2$ …
GATE CSE 2021 Set 1Q53NAT2 marksEasyA five-stage pipeline has stage delays of 150, 120, 150, 160 and 140 nanoseconds. The registers that are used between the pipeline stages have a delay of 5 nanoseconds each. The total time to execute 100 independent instructions on this pipeline, assuming there are no pipeline stalls, is _____ nanoseconds.
GATE CSE 2021 Set 2Q53NAT2 marksMediumConsider a pipelined processor with 5 stages, Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Write Back (WB). Each stage of the pipeline, except the EX stage, takes one cycle. Assume that the ID stage merely decodes the instruction and the register read is performed in the EX…
GATE CSE 2020Q43NAT2 marksMediumConsider a non-pipelined processor operating at 2.5 GHz. It takes 5 clock cycles to complete an instruction. You are going to make a 5-stage pipeline out of this processor. Overheads associated with pipelining force you to operate the pipelined processor at 2 GHz. In a given program, assume that 30% are memory…
GATE CSE 2017 Set 1Q50NAT2 marksMediumInstruction execution in a processor is divided into 5 stages, Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Execute (EX), and Write Back (WB). These stages take 5, 4, 20, 10, and 3 nanoseconds (ns) respectively. A pipelined implementation of the processor requires buffering between each pair of…
GATE CSE 2016 Set 1Q32NAT2 marksMediumThe stage delays in a 4-stage pipeline are 800, 500, 400 and 300 picoseconds. The first stage (with delay 800 picoseconds) is replaced with a functionally equivalent design involving two stages with respective delays 600 and 350 picoseconds. The throughput increase of the pipeline is _________ percent.
GATE CSE 2016 Set 2Q30NAT2 marksMediumSuppose the functions $F$ and $G$ can be computed in 5 and 3 nanoseconds by functional units $U_F$ and $U_G$ , respectively. Given two instances of $U_F$ and two instances of $U_G$ , it is required to implement the computation $F(G(X_i))$ for $1 \le i \le 10$ . Ignoring all other delays, the minimum time…
GATE CSE 2016 Set 2Q33NAT2 marksMediumConsider a 3 GHz (gigahertz) processor with a three-stage pipeline and stage latencies $au_1$ , $au_2$ , and $au_3$ such that $au_1 = 3 au_2/4 = 2 au_3$ . If the longest pipeline stage is split into two pipeline stages of equal latency, the new frequency is _________ GHz, ignoring delays in the pipeline…
GATE CSE 2015 Set 1Q38NAT2 marksMediumConsider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume that there are no stalls in the pipeline.…
GATE CSE 2015 Set 3Q47MCQ2 marksMediumConsider the following code sequence having five instructions $I_1$ to $I_5$ . Each of these instructions has the following format. OP Ri, Rj, Rk where operation OP is performed on contents of registers Rj and Rk and the result is stored in register Ri. $I_1$ : ADD R1, R2, R3 $I_2$ : MUL R7, R1, R3 $I_3$ :…
GATE CSE 2015 Set 3Q51NAT2 marksMediumDiagramConsider the following reservation table for a pipeline having three stages $S_1, S_2$ and $S_3$ . The minimum average latency (MAL) is _______.
GATE CSE 2014 Set 1Q43NAT2 marksMediumConsider a 6-stage instruction pipeline, where all stages are perfectly balanced. Assume that there is no cycle-time overhead of pipelining. When an application is executing on this 6-stage pipeline, the speedup achieved with respect to non-pipelined execution if 25% of the instructions incur 2 pipeline stall cycles…
GATE CSE 2014 Set 3Q9MCQ1 markEasyConsider the following processors (ns stands for nanoseconds). Assume that the pipeline registers have zero latency. P1: Four-stage pipeline with stage latencies 1 ns, 2 ns, 2 ns, 1 ns. P2: Four-stage pipeline with stage latencies 1 ns, 1.5 ns, 1.5 ns, 1.5 ns. P3: Five-stage pipeline with stage latencies 0.5 ns, 1…
GATE CSE 2014 Set 3Q43NAT2 marksHardAn instruction pipeline has five stages, namely, instruction fetch (IF), instruction decode and register fetch (ID/RF), instruction execution (EX), memory access (MEM), and register writeback (WB) with stage latencies 1 ns, 2.2 ns, 2 ns, 1 ns, and 0.75 ns, respectively (ns stands for nanoseconds). To gain in terms of…
GATE CSE 2013Q45MCQ2 marksHardConsider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are 5 ns, 7 ns, 10 ns, 8 ns and 6 ns, respectively. There are intermediate…
GATE CSE 2012Q20MCQ1 markEasyRegister renaming is done in pipelined processors
GATE CSE 2011Q41MCQ2 marksMediumDiagramConsider an instruction pipeline with four stages (S1, S2, S3 and S4) each with combinational circuit only. The pipeline registers are required between each stage and at the end of the last stage. Delays for the stages and for the pipeline registers are as given in the figure. What is the approximate speed up of the…

Topic guide

What does GATE test in Instruction Pipelining?

Instruction pipelining and pipeline hazards are tested extensively with a heavy numerical skew (primarily 2-mark NATs). GATE focuses on evaluating effective CPI and speedup under realistic hazard scenarios (data, control, and structural), calculating clock cycle time from bottleneck stage delays and latch latencies, and analyzing cycle-by-cycle instruction progression with or without operand forwarding. Conceptual items frequently test dependency classifications (RAW, WAR, WAW) and the mechanics of operand bypassing.

Core concepts

5-Stage RISC Pipeline (IF, ID/RF, EX, MEM, WB)
Pipeline Clock Period & Bottleneck Stages
Data Hazards (RAW true dependence, WAR anti-dependence, WAW output dependence)
Operand Forwarding / Bypassing Paths (EX/MEM to EX, MEM/WB to EX)
Load-Use Delay Stalls
Control Hazards and Branch Penalty (Flushing vs Branch Target Buffers / BPU)
Structural Hazards from Multi-cycle Functional Units
Register Renaming to eliminate WAR and WAW Hazards
Reservation Tables, Collision Vectors, and MAL in Non-linear Pipelines
Clock cycle determination via bottleneck stage
Pipeline latency vs throughput
Cycle counting formula (k + n - 1) for n instructions across k stages
Synchronous pipelined execution without hazards
Clock cycle time determination by the bottleneck stage delay
Pipeline register / inter-stage buffer overhead
Pipeline stage decomposition / sub-pipelining
Finite instruction sequence execution time (k + n - 1)
Relative speedup calculation between pipeline architectures

Recurring question patterns

Pipelined vs Non-Pipelined Speedup with Hazard Overheads
common · NAT · 2 marks · 2026, 2024, 2022, 2020
Given instruction mix percentages (ALU, Branch, Memory) and their respective stall penalties or miss rates, calculate effective CPI, instruction execution times, and overall speedup over an unpipelined or baseline processor.
Clock Period, Frequency Optimization, and Stage Splitting
common · NAT · 2 marks · 2025, 2021, 2016, 2014
Determine the clock period from maximum stage latency plus buffer/register overhead, evaluate the effect of splitting bottleneck stages into sub-stages, or calculate throughput changes and execution time for N instructions.
Cycle-by-Cycle Pipeline Trace and Operand Forwarding
common · NAT · 2 marks · 2026, 2021, 2013
Given an explicit sequence of instructions with specific stage latencies or data dependencies, calculate total execution cycles with and without operand forwarding or when resolving branches in specific stages.
Data Dependency Classification and Forwarding Principles
occasional · MSQ · 1 marks · 2026, 2024, 2015, 2012
Analyze an assembly snippet or pipeline architecture to identify RAW (true), WAR (anti), and WAW (output) dependencies, or evaluate true/false conceptual statements regarding forwarding datapaths and register renaming.
Reservation Table and Minimum Average Latency (MAL)
rare · NAT · 2 marks · 2015
Given a stage-time reservation table for a non-linear or multi-function pipeline, identify forbidden latencies, construct the collision vector and state transition diagram, and determine the Minimum Average Latency (MAL).
Ideal Synchronous Pipeline Execution Time
common · NAT · 1 marks · 2023
A $k$ -stage pipeline is specified with individual stage delays and optional buffer overhead. The problem asks for the total time required to execute $n$ independent instructions assuming no stalls, branches, or data dependencies.
Pipeline Stage Splitting and Speedup Comparison
common · NAT · 2 marks · 2017
Given a set of pipeline stage latencies and an intermediate register/buffer delay, evaluate the execution time for a finite number of instructions across a baseline pipeline and an improved pipeline where the bottleneck stage is split into multiple sub-stages, then compute the resulting speedup.

Formulas GATE uses

Pipelined Clock Period

T_{\text{pipe}} = \max(t_1, t_2, \dots, t_k) + t_{\text{overhead}}

Determining processor clock period from stage delays and latch/buffer delays.

Total Execution Time (Ideal Pipeline)

T_{\text{exec}} = (k + n - 1) \times T_{\text{pipe}}

Computing total time to execute $n$ independent instructions on a $k$ -stage pipeline without stalls.

Effective CPI with Pipeline Stalls

\text{CPI}_{\text{eff}} = \text{CPI}_{\text{ideal}} + \sum_{i} (p_i \times \text{stall\_cycles}_i)

Calculating average CPI when instructions encounter data, control, or structural stalls.

Speedup of Pipelined over Non-Pipelined

\text{Speedup} = \frac{\text{Execution Time}_{\text{non-pipe}}}{\text{Execution Time}_{\text{pipe}}} = \frac{\text{CPI}_{\text{non-pipe}} \times T_{\text{non-pipe}}}{\text{CPI}_{\text{pipe}} \times T_{\text{pipe}}} = \frac{\text{CPI}_{\text{non-pipe}} \times f_{\text{pipe}}}{\text{CPI}_{\text{pipe}} \times f_{\text{non-pipe}}}

Comparing throughput/performance between pipelined and non-pipelined processors.

Branch Stall Cycles with Prediction

\text{Stall}_{\text{branch}} = (1 - \text{Accuracy}) \times \text{Penalty}_{\text{mispredict}}

Computing control hazard stalls when a branch prediction unit (BPU) is present.

Structural Hazard Stall Calculation

\text{Stall}_{\text{struct}} = \lceil t_{\text{stage}} / T_{\text{cycle}} \rceil - 1

Calculating stall cycles per instruction when a functional stage takes multiple clock cycles.

Clock Cycle Period

T_{\text{clock}} = \max(t_1, t_2, \dots, t_k) + t_{\text{buffer}}

Used to determine the minimum operating clock period of a synchronous pipeline given individual stage delays and interface latch/buffer delays.

Total Cycles in Ideal Pipeline

\text{Total Cycles} = k + (n - 1)

Used to find the total clock cycles required to process $n$ instructions through a $k$ -stage pipeline without hazards or stalls.

Total Execution Time

\text{Execution Time} = (k + n - 1) \times T_{\text{clock}}

Used to compute the absolute time (in ns, ps, etc.) to execute a batch of $n$ instructions.

Clock Cycle Time with Buffer Delay

t_{\text{cycle}} = \max(t_1, t_2, \dots, t_k) + t_{\text{buffer}}

Used to find the operating clock period of a synchronous pipeline where each stage has a distinct execution delay and pipeline registers introduce overhead.

Total Execution Time for $n$ Instructions in a $k$-Stage Pipeline

T = (k + n - 1) \times t_{\text{cycle}}

Used to calculate the total time taken to execute $n$ independent instructions in a linear $k$ -stage pipeline without hazards or stalls.

Speedup Ratio

\text{Speedup} = \frac{T_{\text{unoptimized}}}{T_{\text{optimized}}} = \frac{(k_1 + n - 1) \times t_{\text{cycle}_1}}{(k_2 + n - 1) \times t_{\text{cycle}_2}}

Used when comparing performance gains of an optimized/split pipeline implementation over a baseline implementation for a fixed task workload.

Examiner traps in Instruction Pipelining

Forgetting latch/register delay when computing clock period after stage splitting.
Applying ideal formula (k+n-1) when dependencies or multi-cycle stages introduce stalls.
Assuming forwarding eliminates all stalls (forgetting the unavoidable 1-cycle stall in load-use data hazards).
Confusing WAR (anti-dependence) and WAW (output dependence) with RAW (true dependence).
Miscalculating branch penalty: forgetting that branch outcome resolution at stage M incurs (M - 1) stall cycles for instruction fetch.
In multi-cycle EX stage stalls, calculating stalls as k instead of (k - 1) per instruction.
Summing up the individual stage delays for every instruction rather than using the bottleneck stage duration (ti) as the clock period.
Off-by-one errors in cycle count (e.g., using k n or k + n instead of k + n - 1).
Forgetting to convert time units (e.g., ns to cycles or vice versa).
Omitting the buffer delay when calculating the pipeline cycle time (tcycle = (ti) instead of (ti) + tbuffer).
Forgetting to update the number of pipeline stages k after splitting a bottleneck stage (e.g., failing to increment k from 5 to 6).
Using asymptotic speedup (tcycle1 / tcycle2) instead of computing the finite instruction count execution time with (k + n - 1).
Rounding speedup prematurely during intermediate steps rather than rounding to two decimal places at the final answer.

How questions are asked

Calculate speedup given instruction mix, branch penalty, and cache miss rates
Find total execution time in microseconds for N instructions with latch delay
Determine new clock frequency after splitting the bottleneck stage
Identify data hazard types (RAW/WAR/WAW) from an assembly code sequence
Cycle-by-cycle schedule comparison (with vs without operand forwarding)
Count total structural stall cycles from a tabular breakdown of stage execution times
Find Minimum Average Latency (MAL) from a reservation table
Calculate total execution time for n instructions given stage delays in nanoseconds.
Numerical calculation of speedup between two pipeline variations for a given instruction batch

Paper trends

Shift from simple formula-based speedup calculations toward multi-hazard models combining branch prediction accuracy, cache miss penalties, and structural hazards.
2026, 2022, 2020, 2014, 2011
Transition of qualitative hazard and forwarding questions from single-correct MCQs to multi-correct MSQs requiring deep understanding of datapath multiplexing.
2024, 2015, 2012
Increased focus on non-uniform multi-cycle execution stages causing structural stalls per instruction type.
2026, 2021
Testing baseline pipeline timing as a clean NAT item focusing on bottleneck stage determination and cycle count arithmetic without hazards.
2023
Questions focus on numerical performance evaluation (NAT) with non-ideal stages and explicit inter-stage buffer overheads rather than theoretical or ideal pipeline assumptions.
2017

Difficulty notes

Easy: Single-concept questions such as finding clock period as max stage delay + latch delay, evaluating $(k+n-1)$ cycles without stalls, or identifying a RAW dependency. Medium: Speedup calculations with mixed stall sources (cache misses, mispredicted branches, data stalls), stage-splitting frequency revisions, or reservation table MAL analysis. Hard: Detailed cycle-by-cycle pipeline traces involving multi-cycle operations (e.g., ADD vs MUL in EX), conditional branches resolved at arbitrary pipeline stages with custom forwarding logic, or multi-stage pipeline redesign ratios.

Instruction Pipelining

25 Qs · since 2011 · 44 marks · 1.8 marks/paperMedium yield

Take topic test

Instruction pipelining and pipeline hazards are tested extensively with a heavy numerical skew (primarily 2-mark NATs). GATE focuses on evaluating effective CPI and speedup under r… Guide

Type

Topic guide

What does GATE test in Instruction Pipelining?

Core concepts

5-Stage RISC Pipeline (IF, ID/RF, EX, MEM, WB)
Pipeline Clock Period & Bottleneck Stages
Data Hazards (RAW true dependence, WAR anti-dependence, WAW output dependence)
Operand Forwarding / Bypassing Paths (EX/MEM to EX, MEM/WB to EX)
Load-Use Delay Stalls
Control Hazards and Branch Penalty (Flushing vs Branch Target Buffers / BPU)
Structural Hazards from Multi-cycle Functional Units
Register Renaming to eliminate WAR and WAW Hazards
Reservation Tables, Collision Vectors, and MAL in Non-linear Pipelines
Clock cycle determination via bottleneck stage
Pipeline latency vs throughput
Cycle counting formula (k + n - 1) for n instructions across k stages
Synchronous pipelined execution without hazards
Clock cycle time determination by the bottleneck stage delay
Pipeline register / inter-stage buffer overhead
Pipeline stage decomposition / sub-pipelining
Finite instruction sequence execution time (k + n - 1)
Relative speedup calculation between pipeline architectures

Recurring question patterns

Pipelined vs Non-Pipelined Speedup with Hazard Overheads
common · NAT · 2 marks · 2026, 2024, 2022, 2020
Given instruction mix percentages (ALU, Branch, Memory) and their respective stall penalties or miss rates, calculate effective CPI, instruction execution times, and overall speedup over an unpipelined or baseline processor.
Clock Period, Frequency Optimization, and Stage Splitting
common · NAT · 2 marks · 2025, 2021, 2016, 2014
Determine the clock period from maximum stage latency plus buffer/register overhead, evaluate the effect of splitting bottleneck stages into sub-stages, or calculate throughput changes and execution time for N instructions.
Cycle-by-Cycle Pipeline Trace and Operand Forwarding
common · NAT · 2 marks · 2026, 2021, 2013
Given an explicit sequence of instructions with specific stage latencies or data dependencies, calculate total execution cycles with and without operand forwarding or when resolving branches in specific stages.
Data Dependency Classification and Forwarding Principles
occasional · MSQ · 1 marks · 2026, 2024, 2015, 2012
Analyze an assembly snippet or pipeline architecture to identify RAW (true), WAR (anti), and WAW (output) dependencies, or evaluate true/false conceptual statements regarding forwarding datapaths and register renaming.
Reservation Table and Minimum Average Latency (MAL)
rare · NAT · 2 marks · 2015
Given a stage-time reservation table for a non-linear or multi-function pipeline, identify forbidden latencies, construct the collision vector and state transition diagram, and determine the Minimum Average Latency (MAL).
Ideal Synchronous Pipeline Execution Time
common · NAT · 1 marks · 2023
A $k$ -stage pipeline is specified with individual stage delays and optional buffer overhead. The problem asks for the total time required to execute $n$ independent instructions assuming no stalls, branches, or data dependencies.
Pipeline Stage Splitting and Speedup Comparison
common · NAT · 2 marks · 2017
Given a set of pipeline stage latencies and an intermediate register/buffer delay, evaluate the execution time for a finite number of instructions across a baseline pipeline and an improved pipeline where the bottleneck stage is split into multiple sub-stages, then compute the resulting speedup.

Formulas GATE uses

Pipelined Clock Period

T_{\text{pipe}} = \max(t_1, t_2, \dots, t_k) + t_{\text{overhead}}

Determining processor clock period from stage delays and latch/buffer delays.

Total Execution Time (Ideal Pipeline)

T_{\text{exec}} = (k + n - 1) \times T_{\text{pipe}}

Computing total time to execute $n$ independent instructions on a $k$ -stage pipeline without stalls.

Effective CPI with Pipeline Stalls

\text{CPI}_{\text{eff}} = \text{CPI}_{\text{ideal}} + \sum_{i} (p_i \times \text{stall\_cycles}_i)

Calculating average CPI when instructions encounter data, control, or structural stalls.

Speedup of Pipelined over Non-Pipelined

\text{Speedup} = \frac{\text{Execution Time}_{\text{non-pipe}}}{\text{Execution Time}_{\text{pipe}}} = \frac{\text{CPI}_{\text{non-pipe}} \times T_{\text{non-pipe}}}{\text{CPI}_{\text{pipe}} \times T_{\text{pipe}}} = \frac{\text{CPI}_{\text{non-pipe}} \times f_{\text{pipe}}}{\text{CPI}_{\text{pipe}} \times f_{\text{non-pipe}}}

Comparing throughput/performance between pipelined and non-pipelined processors.

Branch Stall Cycles with Prediction

\text{Stall}_{\text{branch}} = (1 - \text{Accuracy}) \times \text{Penalty}_{\text{mispredict}}

Computing control hazard stalls when a branch prediction unit (BPU) is present.

Structural Hazard Stall Calculation

\text{Stall}_{\text{struct}} = \lceil t_{\text{stage}} / T_{\text{cycle}} \rceil - 1

Calculating stall cycles per instruction when a functional stage takes multiple clock cycles.

Clock Cycle Period

T_{\text{clock}} = \max(t_1, t_2, \dots, t_k) + t_{\text{buffer}}

Used to determine the minimum operating clock period of a synchronous pipeline given individual stage delays and interface latch/buffer delays.

Total Cycles in Ideal Pipeline

\text{Total Cycles} = k + (n - 1)

Used to find the total clock cycles required to process $n$ instructions through a $k$ -stage pipeline without hazards or stalls.

Total Execution Time

\text{Execution Time} = (k + n - 1) \times T_{\text{clock}}

Used to compute the absolute time (in ns, ps, etc.) to execute a batch of $n$ instructions.

Clock Cycle Time with Buffer Delay

t_{\text{cycle}} = \max(t_1, t_2, \dots, t_k) + t_{\text{buffer}}

Used to find the operating clock period of a synchronous pipeline where each stage has a distinct execution delay and pipeline registers introduce overhead.

Total Execution Time for $n$ Instructions in a $k$-Stage Pipeline

T = (k + n - 1) \times t_{\text{cycle}}

Used to calculate the total time taken to execute $n$ independent instructions in a linear $k$ -stage pipeline without hazards or stalls.

Speedup Ratio

\text{Speedup} = \frac{T_{\text{unoptimized}}}{T_{\text{optimized}}} = \frac{(k_1 + n - 1) \times t_{\text{cycle}_1}}{(k_2 + n - 1) \times t_{\text{cycle}_2}}

Used when comparing performance gains of an optimized/split pipeline implementation over a baseline implementation for a fixed task workload.

Examiner traps in Instruction Pipelining

Forgetting latch/register delay when computing clock period after stage splitting.
Applying ideal formula (k+n-1) when dependencies or multi-cycle stages introduce stalls.
Assuming forwarding eliminates all stalls (forgetting the unavoidable 1-cycle stall in load-use data hazards).
Confusing WAR (anti-dependence) and WAW (output dependence) with RAW (true dependence).
Miscalculating branch penalty: forgetting that branch outcome resolution at stage M incurs (M - 1) stall cycles for instruction fetch.
In multi-cycle EX stage stalls, calculating stalls as k instead of (k - 1) per instruction.
Summing up the individual stage delays for every instruction rather than using the bottleneck stage duration (ti) as the clock period.
Off-by-one errors in cycle count (e.g., using k n or k + n instead of k + n - 1).
Forgetting to convert time units (e.g., ns to cycles or vice versa).
Omitting the buffer delay when calculating the pipeline cycle time (tcycle = (ti) instead of (ti) + tbuffer).
Forgetting to update the number of pipeline stages k after splitting a bottleneck stage (e.g., failing to increment k from 5 to 6).
Using asymptotic speedup (tcycle1 / tcycle2) instead of computing the finite instruction count execution time with (k + n - 1).
Rounding speedup prematurely during intermediate steps rather than rounding to two decimal places at the final answer.

How questions are asked

Calculate speedup given instruction mix, branch penalty, and cache miss rates
Find total execution time in microseconds for N instructions with latch delay
Determine new clock frequency after splitting the bottleneck stage
Identify data hazard types (RAW/WAR/WAW) from an assembly code sequence
Cycle-by-cycle schedule comparison (with vs without operand forwarding)
Count total structural stall cycles from a tabular breakdown of stage execution times
Find Minimum Average Latency (MAL) from a reservation table
Calculate total execution time for n instructions given stage delays in nanoseconds.
Numerical calculation of speedup between two pipeline variations for a given instruction batch

Paper trends

Shift from simple formula-based speedup calculations toward multi-hazard models combining branch prediction accuracy, cache miss penalties, and structural hazards.
2026, 2022, 2020, 2014, 2011
Transition of qualitative hazard and forwarding questions from single-correct MCQs to multi-correct MSQs requiring deep understanding of datapath multiplexing.
2024, 2015, 2012
Increased focus on non-uniform multi-cycle execution stages causing structural stalls per instruction type.
2026, 2021
Testing baseline pipeline timing as a clean NAT item focusing on bottleneck stage determination and cycle count arithmetic without hazards.
2023
Questions focus on numerical performance evaluation (NAT) with non-ideal stages and explicit inter-stage buffer overheads rather than theoretical or ideal pipeline assumptions.
2017