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19 Qs · since 2011 · 29 marks · 1.2 marks/paperMedium yield
Instruction set and addressing modes in GATE CS is consistently tested through instruction word encoding, expanding opcode schemes, addressing mode semantics, and ISA architectural… Guide
ADD R1, #25 // R1 = R1 + 25struct data {
int marks [100];
char grade;
int cnumber;
};
struct data student;
The base address of student is available in register R1. The field student.grade can be accessed efficiently usingLW R1, 20(R2), which during execution reads a 32-bit word from memory and stores it in a 32-bit register R1. The effective address of the memory location is obtained by the addition of a constant 20 and the contents of register R2. Which of the…Topic guide
Instruction set and addressing modes in GATE CS is consistently tested through instruction word encoding, expanding opcode schemes, addressing mode semantics, and ISA architectural principles. Problems evaluate a candidate's ability to calculate bit allocations for opcodes, register specifiers, and immediates, as well as mapping high-level constructs (structs, arrays, pointers) to assembly addressing modes. The topic features a healthy mix of conceptual 1-mark MCQs/MSQs and rigorous 2-mark NATs involving bit calculations and assembly program traces.
Instruction Format Bit Allocation and Immediate Calculation
common · mixed · 1.5 marks · 2025, 2024, 2016, 2014
Given total instruction length, number of distinct instructions, and register counts, determine the field widths (opcode, register, addressing mode, unused) or the maximum immediate/scalar operand value, occasionally incorporating memory alignment constraints (e.g., byte alignment).
Expanding Opcode Technique
common · mixed · 2 marks · 2026, 2020
Calculate the maximum number of distinct instructions for one instruction format given used opcodes in other formats by tracking unused prefix combinations across variable-length opcode fields.
Addressing Mode Identification and HLL Data Structure Mapping
common · MCQ · 1 marks · 2026, 2017, 2011
Identify specific addressing modes (Base-displacement, Index, Indirect, Immediate) from assembly instructions or match addressing modes to high-level language constructs (constants, pointers, struct fields, array indexing).
ISA Fundamentals and Load-Store Execution
common · mixed · 1 marks · 2026, 2025, 2018, 2015
Conceptual evaluation of ISA vs. microarchitecture boundaries (registers vs cache/clock), RISC vs CISC design traits (hardwired control, fixed-length instructions), and synthesizing load-store instruction sequences for high-level operations.
Assembly Code Execution and C-to-Assembly Mapping
occasional · mixed · 2 marks · 2023, 2021
Trace execution of an assembly loop operating on memory arrays to determine final register/memory contents, or fill in missing assembly operands (e.g., shift amounts for scaling, byte offsets, branch labels) matching a C code snippet.
Endianness Arithmetic and Value Comparison
occasional · MSQ · 2 marks · 2021
Given a relation (such as an arithmetic difference) between the numerical values of the same multi-byte integer stored in memory under Little Endian and Big Endian conventions, determine the valid hexadecimal representations.
PC-Relative Branch Offset Calculation
occasional · NAT · 2 marks · 2017
Given a sequence of fixed-size instructions (e.g., 4-byte RISC instructions) and a branch instruction at index i+k targeting index i, compute the signed offset in bytes or words assuming the PC has already advanced to the sequential next instruction.
Register Field Width
Used to find the minimum number of bits required to encode one register operand among architectural registers.
Opcode Field Width
Used when an instruction set requires a fixed-width opcode to distinguish operations.
Max Unsigned Immediate Value
Used to compute the maximum integer representable in an unsigned immediate field of width bits.
Byte-Aligned Memory Size
Used when instructions must be padded to whole byte boundaries in byte-addressable memory.
Expanding Opcode Availability
Used when unused prefixes of bit-length are extended to create opcodes of bit-length .
2-Byte Big-Endian Value
When interpreting a 2-byte integer stored at consecutive addresses where byte is at the lower address (MSB) and byte is at the higher address (LSB).
2-Byte Little-Endian Value
When interpreting a 2-byte integer stored at consecutive addresses where byte is at the lower address (LSB) and byte is at the higher address (MSB).
2-Byte Endianness Value Difference
When relating the numerical difference between little-endian and big-endian representations of the same memory bytes.
PC-Relative Target Address
Used to compute the branch target address when the PC is incremented to point to the instruction immediately following the branch instruction.
Signed Byte Offset Calculation
Used when determining the decimal value to encode in a branch instruction field given instruction size and relative positions.
Instruction format questions evolved from simple 1-mark bit subtractions into multi-format equations with unused/type-specifier bits and linear combinations (e.g., computing ).
2024, 2016, 2014
Introduction of MSQ and multi-option matchings testing fine distinctions between ISA visible state and microarchitectural features.
2026, 2025
Expanding opcode problems shifted from two-type formats (I-type and R-type) to three-tier formats (M-type, R-type, C-type).
2026, 2020
Testing shifted to MSQ formats requiring candidates to solve an algebraic byte constraint () and identify all matching multi-byte hexadecimal patterns.
2021
Focus shifted towards NAT questions requiring signed arithmetic calculation of jump displacements rather than purely theoretical classification of addressing modes.
2017
Easy questions (1 mark) focus on direct formula application (), identifying addressing modes for structs/constants, or distinguishing ISA from microarchitecture. Medium questions (2 marks) involve multi-type expanding opcodes, assembly loop traces with boundary conditions, byte-alignment padding calculations, or C-to-assembly semantic matches.