What are common examiner traps in Instruction Set and Addressing Modes?

Forgetting that 32-bit integer array accesses in byte-addressable memory require byte displacements (scaling index by 4, not 1). Failing to apply the ceiling function ⌈ log2(N) ⌉ when N is not an exact power of 2 (e.g., 50 registers require 6 bits, not 5.64 bits). Conflating ISA features (register file size) with microarchitecture features (cache levels, clock frequency). Forgetting to subtract used opcodes before expanding unused prefixes in expanding opcode problems. Neglecting byte-alignment ceiling ⌈ bits/8 ⌉ before multiplying by total instruction count. Allowing direct memory operands in ALU operations in load-store (RISC) architectures. Confusing written hexadecimal order with memory address order (hex literals are written MSB-first, so standard notation displays B1B0 in little-endian systems where B1 is the MSB). Sign inversion trap: confusing B1 - B0 = +1 with B0 - B1 = +1, leading to selecting inverted byte pairs. Forgetting that 0x00 and 0xFF are valid single-byte values when checking boundary cases like 0x0100. Calculating offset relative to the branch instruction address itself rather than the updated PC (address of the subsequent instruction). Forgetting the negative sign for backward branch offsets. Failing to scale the offset by the instruction length in bytes when offset is specified in byte units rather than word units.

GATE CSE Instruction Set and Addressing Modes PYQs

Medium yield16.3% of Computer Organization and Architecture

Instruction set and addressing modes in GATE CS is consistently tested through instruction word encoding, expanding opcode schemes, addressing mode semantics, a… Read the guide

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Questions: 19
Asked: since 2011
Total marks: 29
Marks / paper: 1.2

19 GATE CSE Instruction Set and Addressing Modes PYQs with solutions, from Computer Organization and Architecture. Browse all GATE CSE PYQs.

Questions

Every official paper that asked this topic, newest first.

What GATE tests in Instruction Set and Addressing Modes

Concepts, patterns, formulas and traps distilled from past papers.

Instruction set and addressing modes in GATE CS is consistently tested through instruction word encoding, expanding opcode schemes, addressing mode semantics, and ISA architectural principles. Problems evaluate a candidate's ability to calculate bit allocations for opcodes, register specifiers, and immediates, as well as mapping high-level constructs (structs, arrays, pointers) to assembly addressing modes. The topic features a healthy mix of conceptual 1-mark MCQs/MSQs and rigorous 2-mark NATs involving bit calculations and assembly program traces.

Core concepts

Instruction word encoding (Opcode, Register fields, Addressing Mode field, Immediate/Displacement)
Expanding opcode encoding for variable-length opcodes
Addressing modes: Immediate, Direct, Register Direct, Register Indirect, Base/Indexed with Displacement, Autoincrement/Autodecrement
ISA vs. Microarchitecture (architectural registers vs. caches, clock speed, pipeline stages)
Load-Store Architecture (RISC principles, memory access strictly via LOAD/STORE)
Byte-addressable memory alignment and pointer arithmetic scaling
Big-Endian vs. Little-Endian memory layout
Least Significant Byte (LSB) and Most Significant Byte (MSB) positioning
Multi-byte integer hexadecimal notation
Byte-level algebraic difference formulation
PC-Relative Addressing Mode
Branch Target Address (BTA) Computation
Instruction Length and Byte Alignment
Relative Displacement (Forward vs. Backward Branching)
Sequential PC Increment Behavior

Recurring question patterns

Instruction Format Bit Allocation and Immediate Calculation
Commonmixed1.5 marks2025, 2024, 2016, 2014
Given total instruction length, number of distinct instructions, and register counts, determine the field widths (opcode, register, addressing mode, unused) or the maximum immediate/scalar operand value, occasionally incorporating memory alignment constraints (e.g., byte alignment).
Expanding Opcode Technique
Commonmixed2 marks2026, 2020
Calculate the maximum number of distinct instructions for one instruction format given used opcodes in other formats by tracking unused prefix combinations across variable-length opcode fields.
Addressing Mode Identification and HLL Data Structure Mapping
CommonMCQ1 marks2026, 2017, 2011
Identify specific addressing modes (Base-displacement, Index, Indirect, Immediate) from assembly instructions or match addressing modes to high-level language constructs (constants, pointers, struct fields, array indexing).
ISA Fundamentals and Load-Store Execution
Commonmixed1 marks2026, 2025, 2018, 2015
Conceptual evaluation of ISA vs. microarchitecture boundaries (registers vs cache/clock), RISC vs CISC design traits (hardwired control, fixed-length instructions), and synthesizing load-store instruction sequences for high-level operations.
Assembly Code Execution and C-to-Assembly Mapping
Occasionalmixed2 marks2023, 2021
Trace execution of an assembly loop operating on memory arrays to determine final register/memory contents, or fill in missing assembly operands (e.g., shift amounts for scaling, byte offsets, branch labels) matching a C code snippet.
Endianness Arithmetic and Value Comparison
OccasionalMSQ2 marks2021
Given a relation (such as an arithmetic difference) between the numerical values of the same multi-byte integer stored in memory under Little Endian and Big Endian conventions, determine the valid hexadecimal representations.
PC-Relative Branch Offset Calculation
OccasionalNAT2 marks2017
Given a sequence of fixed-size instructions (e.g., 4-byte RISC instructions) and a branch instruction at index i+k targeting index i, compute the signed offset in bytes or words assuming the PC has already advanced to the sequential next instruction.

Formulas GATE uses

k = \lceil \log_2(N_{\text{registers}}) \rceil

Used to find the minimum number of bits required to encode one register operand among $N_{\text{registers}}$ architectural registers.

Opcode Field Width

b_{\text{opcode}} = \lceil \log_2(N_{\text{instructions}}) \rceil

Used when an instruction set requires a fixed-width opcode to distinguish $N_{\text{instructions}}$ operations.

Max Unsigned Immediate Value

\text{Max Value} = 2^k - 1

Used to compute the maximum integer representable in an unsigned immediate field of width $k$ bits.

Byte-Aligned Memory Size

\text{Bytes per instruction} = \left\lceil \frac{\text{Instruction Bits}}{8} \right\rceil

Used when instructions must be padded to whole byte boundaries in byte-addressable memory.

Expanding Opcode Availability

\text{Available}_{i+1} = (\text{Total}_{i} - \text{Used}_{i}) \times 2^{(L_{i+1} - L_i)}

Used when unused prefixes of bit-length $L_i$ are extended to create opcodes of bit-length $L_{i+1}$ .

2-Byte Big-Endian Value

V_{\text{BE}} = 256 \cdot B_0 + B_1

When interpreting a 2-byte integer stored at consecutive addresses where byte $B_0$ is at the lower address (MSB) and byte $B_1$ is at the higher address (LSB).

2-Byte Little-Endian Value

V_{\text{LE}} = 256 \cdot B_1 + B_0

When interpreting a 2-byte integer stored at consecutive addresses where byte $B_0$ is at the lower address (LSB) and byte $B_1$ is at the higher address (MSB).

2-Byte Endianness Value Difference

V_{\text{LE}} - V_{\text{BE}} = 255 \cdot (B_1 - B_0)

When relating the numerical difference between little-endian and big-endian representations of the same memory bytes.

PC-Relative Target Address

\text{Target Address} = \text{PC}_{\text{updated}} + \text{Offset}

Used to compute the branch target address when the PC is incremented to point to the instruction immediately following the branch instruction.

Signed Byte Offset Calculation

\text{Offset} = \text{Target Address} - \text{Address of Next Instruction}

Used when determining the decimal value to encode in a branch instruction field given instruction size and relative positions.

Examiner traps in Instruction Set and Addressing Modes

Forgetting that 32-bit integer array accesses in byte-addressable memory require byte displacements (scaling index by 4, not 1).
Failing to apply the ceiling function ⌈ log2(N) ⌉ when N is not an exact power of 2 (e.g., 50 registers require 6 bits, not 5.64 bits).
Conflating ISA features (register file size) with microarchitecture features (cache levels, clock frequency).
Forgetting to subtract used opcodes before expanding unused prefixes in expanding opcode problems.
Neglecting byte-alignment ceiling ⌈ bits/8 ⌉ before multiplying by total instruction count.
Allowing direct memory operands in ALU operations in load-store (RISC) architectures.
Confusing written hexadecimal order with memory address order (hex literals are written MSB-first, so standard notation displays B1B0 in little-endian systems where B1 is the MSB).
Sign inversion trap: confusing B1 - B0 = +1 with B0 - B1 = +1, leading to selecting inverted byte pairs.
Forgetting that 0x00 and 0xFF are valid single-byte values when checking boundary cases like 0x0100.
Calculating offset relative to the branch instruction address itself rather than the updated PC (address of the subsequent instruction).
Forgetting the negative sign for backward branch offsets.
Failing to scale the offset by the instruction length in bytes when offset is specified in byte units rather than word units.

How questions are asked

Compute bit-field width or immediate range (NAT)
Multi-tier expanding opcode maximization (NAT/MCQ)
Match addressing mode to high-level programming language construct (MCQ)
Identify architectural characteristics vs microarchitectural implementations (MSQ/MCQ)
Synthesize load-store instruction sequence for arithmetic expressions (MCQ)
Assembly loop trace with memory address updates (NAT)
Fill-in-the-blank operands for C-to-assembly compiler mapping (MCQ)
Multi-select identification of hexadecimal values matching endian arithmetic conditions
Memory-dump byte layout translation to integer/hex representation
Instruction sequence analysis to compute signed numerical branch offset (NAT)
Effective address calculation given register values and addressing mode specifications

Paper trends

Instruction format questions evolved from simple 1-mark bit subtractions into multi-format equations with unused/type-specifier bits and linear combinations (e.g., computing $X + 2Y + Z$ ).
2024, 2016, 2014
Introduction of MSQ and multi-option matchings testing fine distinctions between ISA visible state and microarchitectural features.
2026, 2025
Expanding opcode problems shifted from two-type formats (I-type and R-type) to three-tier formats (M-type, R-type, C-type).
2026, 2020
Testing shifted to MSQ formats requiring candidates to solve an algebraic byte constraint ( $B_1 - B_0 = k$ ) and identify all matching multi-byte hexadecimal patterns.
2021
Focus shifted towards NAT questions requiring signed arithmetic calculation of jump displacements rather than purely theoretical classification of addressing modes.
2017

Difficulty notes

Easy questions (1 mark) focus on direct formula application ( $ext{Instruction length} - ext{fields} = ext{Immediate}$ ), identifying addressing modes for structs/constants, or distinguishing ISA from microarchitecture. Medium questions (2 marks) involve multi-type expanding opcodes, assembly loop traces with boundary conditions, byte-alignment padding calculations, or C-to-assembly semantic matches.