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Cache Memory and Hierarchy

GATE CSE 2023 · Q42

MCQ2 marksMedium

Time

A 4 kilobyte (KB) byte-addressable memory is realized using four 1 KB memory blocks. Two input address lines (IA4 and IA3) are connected to the chip select (CS) port of these memory blocks through a decoder as shown in the figure. The remaining ten input address lines from IA11–IA0 are connected to the address port of these blocks. The chip select (CS) is active high. The input memory addresses (IA11–IA0), in decimal, for the starting locations (Addr=0) of each block (indicated as X1, X2, X3, X4 in the figure) are among the options given below. Which one of the following options is CORRECT?

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Solution

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Official answer: C) (0, 8, 16, 24)

Cache Memory and Hierarchy

To find the starting address in decimal for each 1 KB memory block (indicated as X1, X2, X3, X4), consider the 12-bit input address IA11–IA0\text{IA11}–\text{IA0}:

  1. Starting location condition: For the starting location of each memory block, the internal address is Addr=0\text{Addr} = 0. Since the remaining 10 address lines (IA11–IA5 and IA2–IA0) form the 10-bit Addr\text{Addr} input, all these 10 lines must be 00:

    IA11=IA10=IA9=IA8=IA7=IA6=IA5=0\text{IA11} = \text{IA10} = \text{IA9} = \text{IA8} = \text{IA7} = \text{IA6} = \text{IA5} = 0
    IA2=IA1=IA0=0\text{IA2} = \text{IA1} = \text{IA0} = 0
  2. Decoder inputs: The 2-to-4 decoder selects the memory blocks based on lines IA4\text{IA4} (connected to A1A_1) and IA3\text{IA3} (connected to A0A_0):

    • Block X1 (selected by Q0Q_0):(A1,A0)=(0,0)  ⟹  IA4=0,IA3=0(A_1, A_0) = (0, 0) \implies \text{IA4} = 0, \text{IA3} = 0

      Address=(0000000  00  000)2=0\text{Address} = (0000000\;00\;000)_2 = 0
    • Block X2 (selected by Q1Q_1):(A1,A0)=(0,1)  ⟹  IA4=0,IA3=1(A_1, A_0) = (0, 1) \implies \text{IA4} = 0, \text{IA3} = 1

      Address=(0000000  01  000)2=23=8\text{Address} = (0000000\;01\;000)_2 = 2^3 = 8
    • Block X3 (selected by Q2Q_2):(A1,A0)=(1,0)  ⟹  IA4=1,IA3=0(A_1, A_0) = (1, 0) \implies \text{IA4} = 1, \text{IA3} = 0

      Address=(0000000  10  000)2=24=16\text{Address} = (0000000\;10\;000)_2 = 2^4 = 16
    • Block X4 (selected by Q3Q_3):(A1,A0)=(1,1)  ⟹  IA4=1,IA3=1(A_1, A_0) = (1, 1) \implies \text{IA4} = 1, \text{IA3} = 1

      Address=(0000000  11  000)2=24+23=24\text{Address} = (0000000\;11\;000)_2 = 2^4 + 2^3 = 24

Thus, the starting addresses for blocks X1, X2, X3, and X4 are (0,8,16,24)(0, 8, 16, 24), which corresponds to Option (C).

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This Cache Memory and Hierarchy previous year question is Q42 of the GATE CSE 2023 paper. Find more GATE CSE PYQs on Cache Memory and Hierarchy in Computer Organization and Architecture, or browse all GATE CSE PYQs.

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Cache Memory and Hierarchy in GATE CSE

Cache Memory and Hierarchy has 47 GATE CSE PYQs across 23 papers from 2011 to 2026. 16 of them are 2-mark MCQs like this one, and GATE CSE 2023 has 2.

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GateAI solution cardGATE CSE 2023 · Q42 · MCQ

A 4 kilobyte (KB) byte-addressable memory is realized using four 1 KB memory blocks. Two input address lines (IA4 and IA3) are connected to the chip select (CS) port of these memory blocks through a decoder as shown in the figure. The remaining ten input address lines from IA11–IA0 are connected to the address port of these blocks. The chip select (CS) is active high. The input memory addresses (IA11–IA0), in decimal, for the starting locations (Addr=0) of each block (indicated as X1, X2, X3, X4 in the figure) are among the options given below. Which one of the following options is CORRECT?

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