What are common examiner traps in Cache Memory and Hierarchy?

Confusing word addressability with byte addressability (e.g., assuming 1 address = 1 byte when word size is given as 2 or 4 bytes). Misinterpreting local miss rate vs. global miss rate in multi-level caches (e.g., using misses per 1000 instructions as local miss rate without dividing by L1 misses). Adding L1 access time twice when formula uses hierarchical format vs miss penalty format. Assuming Write-Through caches have dirty bits, or forgetting that dirty blocks in Write-Back are only written back upon eviction (not on the initial write hit). Forgetting that compulsory misses occur strictly on the first global reference to a distinct block, not on subsequent conflicts in a looped trace. Forgetting that increasing associativity k → 2k keeps Tag + Index constant, thus increasing tag bits by 1 bit and reducing index bits by 1 bit. Multiplying tag directory entry size by number of sets instead of total number of cache lines (blocks). Confusing number of sets v with associativity k in modulo mapping (j mod v vs j mod k). Overlooking extra status bits (multiple valid bits, dirty bits, replacement bits) when computing tag directory size. Assuming write-allocate must strictly be paired with write-through (in reality, write-allocate is standard for write-back). Forgetting that write-through caches never hold dirty lines, so evictions never trigger dirty writebacks. Confusing word length (e.g. 32-bit architecture) with the physical address size when main memory size is explicitly specified (e.g., 16 MB implies a 24-bit address, not 32-bit). Dividing cache size by set associativity before dividing by block size (or forgetting to divide total lines by P-way associativity to get set count). Misaligning hexadecimal digits when the set index or tag does not align on 4-bit nibble boundaries, requiring manual binary extraction of intermediate bits. Forgetting to multiply the metadata per line by the total number of lines (instead of number of sets) when calculating total tag directory size. Assuming the decoder is always connected to the Most Significant Bits (MSBs), which leads to standard contiguous block starting addresses like (0, 1024, 2048, 3072). Ignoring the weights of the specific bit positions connected to the decoder inputs (e.g., treating bit IA3 as weight 1 instead of weight 23 = 8). Confusing the order of decoder input selection lines (e.g., A1 vs A0 connections causing swapped outputs). Forgetting the top-level enable decoder in decoder trees (e.g., counting only the 4 second-level decoders instead of 1 + 4 = 5 decoders in 2013). Confusing the number of total chips with the number of row selection outputs when sizing the decoder tree. Multiplying DRAM refresh time by the total number of chips instead of the number of internal rows in a single chip refreshed simultaneously (2018). Misinterpreting given L2/Main Memory access times as incremental access times versus cumulative miss penalties (2025). Confusing multiplexers (k:1 data selector) with decoders (k:2k address line expander) when identifying datapath block diagrams (2022). Unit conversion errors between seconds, nanoseconds (10-9 s), and clock frequency (GHz/MHz) Failing to multiply individual instruction class counts by their specific CPIs before summing Confusing total instruction count with total cycle count Assuming index bits exist in a fully associative cache (forgetting that fully associative implies 0 index bits / 1 set). Confusing total cache lines with sets when dealing with different associativity levels. Incorrectly interpreting active-low (bubble) inputs on logic gates when computing fixed high-order address bits. Off-by-one errors in binary-to-hexadecimal grouping when converting the maximum address (all 1s in unconstrained lines). Inverting the frequency ratio: forgetting that execution time is inversely proportional to clock frequency (T 1/f). Miscalculating percentage decrease vs increase (e.g., taking 25\% less time as dividing by 1.25 instead of multiplying by 0.75). Assuming instruction count changes when identical ISAs and inputs are explicitly stated.

GATE CSE Cache Memory and Hierarchy PYQs

High yield46.1% of Computer Organization and Architecture

Memory hierarchy and cache mapping is one of the highest-yield, most quantitative topics in GATE Computer Science, regularly tested through 2-mark NAT and MSQ q… Read the guide

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Questions: 47
Asked: since 2011
Total marks: 82
Marks / paper: 3.3

47 GATE CSE Cache Memory and Hierarchy PYQs with solutions, from Computer Organization and Architecture. Browse all GATE CSE PYQs.

Questions

Every official paper that asked this topic, newest first.

What GATE tests in Cache Memory and Hierarchy

Concepts, patterns, formulas and traps distilled from past papers.

Memory hierarchy and cache mapping is one of the highest-yield, most quantitative topics in GATE Computer Science, regularly tested through 2-mark NAT and MSQ questions. GATE focuses heavily on bit-level address field decomposition (Tag, Set/Line Index, Block Offset) across direct, set-associative, and fully-associative caches, as well as multi-level hierarchical Average Memory Access Time (AMAT) calculations. Recent years have increased the emphasis on multi-select questions (MSQs) tracing reference sequences for eviction behavior and comparing write-back versus write-through policies.

Core concepts

Direct, fully-associative, and k-way set-associative cache mapping
Physical vs. Virtual indexing and Tagging (Page coloring for aliasing)
Hierarchical vs. Simultaneous memory access models
Average Memory Access Time (AMAT) and stall cycles per instruction
Separate Instruction (I-Cache) and Data (D-Cache) hierarchies
Write-Through with No-Write Allocate vs. Write-Back with Write Allocate
Dirty (Modified) bit and Valid bit mechanics during hit/miss/eviction
Block replacement algorithms (LRU, FIFO) and reference string simulation
Compulsory (cold), Capacity, and Conflict misses
Memory interleaving, bank cycle time, and bus bottleneck analysis
Magnetic disk drive geometry and capacity calculations
Address decomposition: Tag, Set Index, and Word/Byte Offset fields
Cache organization: k-way Set-Associative, Direct-Mapped, and Fully-Associative architectures
Cache tag directory overhead: Tag size, Valid bits, Dirty/Modified bits, and Replacement policy bits
Set mapping arithmetic using modulo operations (j mod v)
Write update policies: Write-through vs. Write-back and dirty bit behavior
Write miss policies: Write-allocate vs. No-write-allocate pairing and multilevel inclusivity
Address division into Tag, Set/Line Index, and Block Offset
Direct-mapped vs. P-way set-associative cache geometry
Metadata bits per line (Tag bits, Valid bit, Modified/Dirty bit in write-back cache)
Hexadecimal address bit-slicing and masking to extract index and tag
Byte addressability vs. word length distinctions
Address line partitioning (Chip Select decoding vs. Internal Memory Address)
Decoder logic (Active High/Active Low Chip Select)
Non-contiguous bit decoding (interleaving / stride addressing caused by middle-bit chip selection)
Starting and ending addresses of memory modules
Memory matrix organization (rows vs columns of RAM chips)
Hierarchical address decoder construction using enable inputs
DRAM row-by-row refresh timing, refresh period, and bandwidth overhead
Address decoder sizing (k : 2k) versus Multiplexer routing (k : 1)
Code word / control word bit allocation for memory/register select
Multi-level memory hierarchy (L1, L2, Main Memory) AMAT and miss rates
Cycles Per Instruction (CPI) per instruction class
Total clock cycle computation from instruction mix
CPU execution time and clock period relationship
Unit conversion between seconds and nanoseconds
Fully associative, direct, and set-associative cache mapping
Physical address breakdown (Tag, Index, Block Offset)
Byte-addressable memory organization
Memory chip interfacing and address decoding
Active-high and active-low chip select logic
Hexadecimal-to-binary address range conversion
CPU Execution Time equation
Cycles Per Instruction (CPI)
Clock frequency (f) vs Clock cycle time ( = 1/f)
Instruction count invariance across identical instruction sets and inputs
Relative performance percentage scaling

Recurring question patterns

Cache Address Field Decomposition and Tag Sizing
CommonNAT2 marks2026, 2025, 2023, 2021
Given physical address size, cache capacity, block size, and associativity (or variations where one parameter is unknown or parameterized by variables), calculate the width of Tag, Set Index, or Offset bits, or total tag memory required.
Multi-Level Cache AMAT and CPI Stall Analysis
CommonNAT2 marks2025, 2024, 2022, 2017
Given L1/L2 access times, local/global hit rates, and main memory miss penalties (often separated into I-cache and D-cache or read/write distributions), calculate AMAT, effective CPI, or minimum required hit rate after optimization.
Address Trace Simulation and Cache Conflict/Hit Analysis
CommonMSQ2 marks2026, 2022, 2017, 2014
Given a sequence of hex addresses or block numbers accessed in a loop over a specific cache organization, trace compulsory vs conflict misses, hit/miss outcomes for specific references, and final cache contents.
Write Policy Conceptual Analysis
OccasionalMSQ2 marks2024, 2022
Evaluate architectural assertions regarding Write-Back vs. Write-Through policies, dirty bit necessity, eviction penalties on read/write misses, and memory bus traffic.
Memory Interleaving and Secondary Storage Geometry
OccasionalNAT2 marks2024, 2016, 2014
Calculate throughput/initiation rates in multi-module interleaved memory systems or solve for disk geometry parameters (cylinders, surfaces, sectors) from capacity constraints.
Cache Address Breakdown and Tag Directory Size Calculation
CommonMCQ2 marks2012
Given physical address size, cache capacity, associativity, and block size, calculate the number of tag bits and the total size in bits/Kbits of the tag directory (including status bits like valid, modified/dirty, replacement bits).
Algebraic Block-to-Line/Set Mapping Formulation
OccasionalMCQ1 marks2013
Formulating the exact cache line index range or set index algebraically for a memory block $j$ in a $k$ -way set associative cache with $v$ sets where lines are ordered consecutively.
Cache Write and Allocation Policy Analysis
OccasionalMCQ2 marks2021
Multi-statement verification evaluating properties of write-through vs. write-back policies (dirty line handling, writebacks on read/write misses) and their pairings with write-allocate vs. no-write-allocate policies in single/multilevel caches.
Hexadecimal Address Mapping and Set/Line Index Extraction
CommonMCQ2 marks2020, 2015
Given physical memory size, cache parameters (cache size, associativity, block size), and one or more hexadecimal addresses, determine field bit-widths (Tag, Index, Offset) and identify which set/line the addresses map to or extract their exact hexadecimal Tag and Index values.
Cache Controller Metadata and Tag Directory Size Calculation
OccasionalMCQ2 marks2011
Given cache capacity, block size, address length, and mapping scheme along with status bits (valid bit, dirty/modified bit for write-back), determine the total storage required for metadata (tag directory size).
Decoder-Based Chip Select and Address Mapping
RareMCQ2 marks2023
A system memory of size $N$ is built using smaller memory blocks selected by a decoder driven by a subset of system address lines. Candidates determine the starting/ending addresses or address range of specific memory chips based on which bit positions drive the decoder versus the chip internal address lines.
Memory Chip Expansion and Decoder Tree Design
OccasionalMCQ2 marks2013
Constructing a target memory capacity and word length using smaller RAM/ROM chips, determining row/column organization, and calculating the exact number of smaller decoders (with enable lines) required to form the address decoding tree.
DRAM Refresh Overhead and Bandwidth Availability
OccasionalNAT1 marks2018
Given the number of memory cell rows in a DRAM chip, time per row refresh operation, and refresh period, calculating the total refresh time overhead and the remaining percentage of time available for read/write operations.
Memory & Register Interfacing Logic Identification
OccasionalMCQ2 marks2022
Determining the required addressing components (e.g., $n:2^n$ decoders) and data path routing units (e.g., $k:1$ multiplexers) for interfacing distinct memory segments and register files given word sizes and instruction/code word layouts.
Hierarchical Average Memory Access Time (AMAT)
OccasionalNAT2 marks2025
Computing the overall AMAT across a multi-level hierarchy (L1 cache, L2 cache, Main Memory) given access times, hit rates, or miss penalties at each level in simultaneous or hierarchical access configurations.
Instruction Mix and Clock Cycle Time Calculation
CommonNAT2 marks2025
Given an instruction breakdown by category with respective CPIs/cycle counts and total execution time, compute the total clock cycles and solve for the clock cycle duration (in ns) or clock frequency (in MHz/GHz).
Cache Address Field Division
CommonMCQ1 marks2019
Given cache parameters (cache size, block size, associativity) and main memory address width, compute the number of bits allocated to Tag, Set/Index, and Word/Byte offset fields.
Chip Select Address Decoding
CommonMCQ1 marks2019
Given a logic gate circuit (e.g., AND/NAND with inverted inputs) driving the Chip Select (CS) line using higher-order address lines, determine the enabled memory address range in hexadecimal.
Comparative CPU Performance & Execution Time Ratio
CommonNAT2 marks2014
Two processors executing the same instruction set/program with relative differences in execution time and CPI are compared to compute an unknown processor metric (such as clock frequency or cycle time).

Formulas GATE uses

Cache Line Count

\text{Number of Lines } (N) = \frac{\text{Cache Capacity}}{\text{Block Size}}

Determining total cache lines before calculating index bits or set counts.

Number of Sets in $k$-Way Set Associative Cache

\text{Number of Sets } (S) = \frac{N}{k} = \frac{\text{Cache Capacity}}{k \times \text{Block Size}}

Determining set index bits in set-associative cache mappings.

Address Field Partitioning

\text{Address Bits} = \text{Tag Bits} + \log_2(S) + \log_2(\text{Block Size in Bytes})

Calculating tag size or verifying total physical address width.

Tag Invariance with Block Size

\text{Set Index Bits} + \text{Block Offset Bits} = \log_2\left(\frac{\text{Cache Capacity}}{k}\right)

Solving for tag width when block size is unknown or variable.

Total Tag Memory Overhead

\text{Total Tag Storage} = N \times (\text{Tag Bits} + \text{Valid Bit} + \text{Dirty Bit})

Calculating the total hardware memory needed to store cache tags and status bits.

Hierarchical Two-Level AMAT

\text{AMAT} = T_{L1} + (1 - H_{L1}) \times \left( T_{L2} + (1 - H_{L2}) \times T_{MM} \right)

Calculating average access time when miss penalties are resolved hierarchically level-by-level.

CPI with Split Memory Stalls

\text{CPI}_{\text{actual}} = \text{CPI}_{\text{ideal}} + (1 \times m_I \times P_I) + (f_{\text{data}} \times m_D \times P_D)

Calculating processor stall overhead for separate instruction and data caches.

Hard Disk Capacity

\text{Capacity} = \text{Cylinders} \times \text{Surfaces} \times \frac{\text{Sectors}}{\text{Track}} \times \frac{\text{Bytes}}{\text{Sector}}

Solving for disk geometry parameters from total formatted capacity.

Block Offset Bits

\text{Block Offset} = \log_2(\text{Block Size in Bytes})

Determining word/byte offset bits within a cache block from block capacity.

Number of Sets and Set Index Bits

\text{Number of Sets } (v) = \frac{\text{Cache Size}}{\text{Block Size} \times k}, \quad \text{Set Index Bits} = \log_2(v)

Finding set index width in a $k$ -way set associative cache.

Tag Bits Calculation

\text{Tag Bits} = \text{Physical Address Bits} - (\text{Set Index Bits} + \text{Block Offset Bits})

Finding address tag width in set-associative cache memory.

Tag Directory Entry and Total Directory Size

$\text{Entry Size} = \text{Tag Bits} + \text{Valid Bits} + \text{Dirty Bits} + \text{Replacement Bits}$ $\text{Tag Directory Size} = (\text{Total Cache Lines}) \times \text{Entry Size}$

Computing total storage overhead of the tag array.

Set-Associative Line Index Range for Block $j$

\text{Line Range} = \left[ (j \bmod v) \times k, \; (j \bmod v) \times k + (k - 1) \right]

Mapping main memory block $j$ to linear cache line indices in a $k$ -way set associative cache with $v$ sets.

Block Offset Bit-Width

\text{Offset bits} = \log_2(\text{Block Size in bytes})

Determining word/byte offset within a cache block for byte-addressable memories.

Number of Lines / Sets

\text{Number of Sets} = \frac{\text{Cache Size}}{\text{Block Size} \times P}

Calculating number of index lines/sets for a $P$ -way set-associative cache ( $P=1$ for direct-mapped).

Tag Bit-Width

\text{Tag bits} = \text{Physical Address bits} - (\text{Index bits} + \text{Offset bits})

Determining the number of bits allocated to the tag field.

Total Metadata Size

\text{Total Metadata} = \text{Number of Cache Lines} \times (\text{Tag bits} + \text{Valid bits} + \text{Dirty bits})

Calculating the total storage overhead at the cache controller for write-back or write-through caches.

Address Value from Bit Positions

\text{Address} = \sum_{i=0}^{n-1} b_i \cdot 2^i

Used to compute the physical decimal/hex starting address when specific address bits $b_i$ are fixed by decoder selection lines and the internal chip address lines are set to zero.

Total Memory Chips Required

\text{Chips} = \frac{\text{Target Capacity} \times \text{Target Word Size}}{\text{Chip Capacity} \times \text{Chip Word Size}}

Determining the total number of basic RAM/ROM chips needed to build a target memory matrix (2013).

Decoder Tree Hierarchy Count

\text{Total Decoders of size } k \times 2^k \text{ for } N \text{ outputs} = 1 + \frac{N}{2^k}

Used when a single first-level $k \times 2^k$ decoder enables $N/2^k$ second-level decoders to produce $N$ select lines (2013).

DRAM Refresh Overhead Time

T_{\text{refresh total}} = N_{\text{rows}} \times t_{\text{row\_refresh}}

Calculating the total time occupied by refreshing all memory rows within one refresh cycle period (2018).

Available Time Percentage for Memory R/W

\text{Available \%} = \left(1 - \frac{T_{\text{refresh total}}}{T_{\text{period}}}\right) \times 100\%

Finding the percentage of operating time remaining for processor memory access after subtracting refresh overhead (2018).

Address Bits for $N$-Word Memory

\text{Address Bits } k = \log_2(N)

Determining the decoder size ( $k : 2^k$ ) needed to uniquely address $N$ memory words or registers (2022).

Hierarchical AMAT (2-Level Cache + Main Memory)

\text{AMAT} = H_1 T_1 + (1 - H_1)[H_2 T_2 + (1 - H_2) T_m]

Computing average memory access time when lower-level access times already subsume miss detection penalties from upper levels (2025).

Total Clock Cycles

\text{Total Cycles} = \sum_{i} (N_i \times \text{CPI}_i)

Used to find total clock cycles when instruction count $N_i$ and CPI for each instruction type $i$ are given.

CPU Execution Time

\text{Execution Time} = \text{Total Cycles} \times T_{\text{clk}} = \frac{\text{Total Cycles}}{f}

Used to solve for clock period $T_{\text{clk}}$ or frequency $f$ given overall runtime.

Block Offset Calculation

\text{Offset bits} = \log_2(\text{Block Size in bytes})

Determining the number of bits required to address a specific byte within a cache line.

Cache Index / Set Bits

\text{Index bits} = \log_2(\text{Number of Sets})

Used in direct mapped and set-associative caches. For fully associative cache, Number of Sets = 1, so Index bits = 0.

Tag Bit Allocation

\text{Tag bits} = \text{Address bits} - (\text{Index bits} + \text{Offset bits})

Finding the remaining bits in the memory address used for tag comparison.

Processor Time Ratio

\frac{T_2}{T_1} = \left(\frac{I_2}{I_1}\right) \times \left(\frac{\text{CPI}_2}{\text{CPI}_1}\right) \times \left(\frac{f_1}{f_2}\right)

Used when comparing execution time differences between two machines executing the same workload.

Examiner traps in Cache Memory and Hierarchy

Confusing word addressability with byte addressability (e.g., assuming 1 address = 1 byte when word size is given as 2 or 4 bytes).
Misinterpreting local miss rate vs. global miss rate in multi-level caches (e.g., using misses per 1000 instructions as local miss rate without dividing by L1 misses).
Adding L1 access time twice when formula uses hierarchical format vs miss penalty format.
Assuming Write-Through caches have dirty bits, or forgetting that dirty blocks in Write-Back are only written back upon eviction (not on the initial write hit).
Forgetting that compulsory misses occur strictly on the first global reference to a distinct block, not on subsequent conflicts in a looped trace.
Forgetting that increasing associativity k → 2k keeps Tag + Index constant, thus increasing tag bits by 1 bit and reducing index bits by 1 bit.
Multiplying tag directory entry size by number of sets instead of total number of cache lines (blocks).
Confusing number of sets v with associativity k in modulo mapping (j mod v vs j mod k).
Overlooking extra status bits (multiple valid bits, dirty bits, replacement bits) when computing tag directory size.
Assuming write-allocate must strictly be paired with write-through (in reality, write-allocate is standard for write-back).
Forgetting that write-through caches never hold dirty lines, so evictions never trigger dirty writebacks.
Confusing word length (e.g. 32-bit architecture) with the physical address size when main memory size is explicitly specified (e.g., 16 MB implies a 24-bit address, not 32-bit).
Dividing cache size by set associativity before dividing by block size (or forgetting to divide total lines by P-way associativity to get set count).
Misaligning hexadecimal digits when the set index or tag does not align on 4-bit nibble boundaries, requiring manual binary extraction of intermediate bits.
Forgetting to multiply the metadata per line by the total number of lines (instead of number of sets) when calculating total tag directory size.
Assuming the decoder is always connected to the Most Significant Bits (MSBs), which leads to standard contiguous block starting addresses like (0, 1024, 2048, 3072).
Ignoring the weights of the specific bit positions connected to the decoder inputs (e.g., treating bit IA3 as weight 1 instead of weight 23 = 8).
Confusing the order of decoder input selection lines (e.g., A1 vs A0 connections causing swapped outputs).
Forgetting the top-level enable decoder in decoder trees (e.g., counting only the 4 second-level decoders instead of 1 + 4 = 5 decoders in 2013).
Confusing the number of total chips with the number of row selection outputs when sizing the decoder tree.
Multiplying DRAM refresh time by the total number of chips instead of the number of internal rows in a single chip refreshed simultaneously (2018).
Misinterpreting given L2/Main Memory access times as incremental access times versus cumulative miss penalties (2025).
Confusing multiplexers (k:1 data selector) with decoders (k:2k address line expander) when identifying datapath block diagrams (2022).
Unit conversion errors between seconds, nanoseconds (10-9 s), and clock frequency (GHz/MHz)
Failing to multiply individual instruction class counts by their specific CPIs before summing
Confusing total instruction count with total cycle count
Assuming index bits exist in a fully associative cache (forgetting that fully associative implies 0 index bits / 1 set).
Confusing total cache lines with sets when dealing with different associativity levels.
Incorrectly interpreting active-low (bubble) inputs on logic gates when computing fixed high-order address bits.
Off-by-one errors in binary-to-hexadecimal grouping when converting the maximum address (all 1s in unconstrained lines).
Inverting the frequency ratio: forgetting that execution time is inversely proportional to clock frequency (T 1/f).
Miscalculating percentage decrease vs increase (e.g., taking 25\% less time as dividing by 1.25 instead of multiplying by 0.75).
Assuming instruction count changes when identical ISAs and inputs are explicitly stated.

How questions are asked

NAT: Calculate tag field bit width from cache/memory sizing parameters
NAT: Compute multi-level AMAT or effective CPI with stall penalties
MSQ: Trace hex memory references in a loop to identify hit/miss/eviction states
MSQ: Identify correct/incorrect statements regarding Write-Back vs. Write-Through cache policies
NAT: Reverse-engineer cache size or associativity from mapping constraints on given address values
NAT: Multi-module interleaved memory initiation count in a given time window
Address field bit width calculation
Tag directory memory overhead calculation
Algebraic formula selection for line/set mapping
Multi-statement evaluation on write policies and multi-level cache behavior
Calculate total tag/metadata memory overhead in bits/bytes
Find Tag and Line Index values in hexadecimal for a given address
Match given multiple hexadecimal addresses to identical or different cache sets
Schematic diagram analysis with decoder and memory block connections
Determining starting/ending decimal or hexadecimal addresses for memory modules
Count component units (decoders, chips) to build a larger target memory
Calculate time overhead or available bandwidth percentage (NAT)
Block diagram component identification matching control word bits
Multi-level AMAT calculation with hit rates and access times
Table-based instruction mix NAT calculation
Clock period derivation from program execution time
Calculate Tag/Index/Offset bit counts from cache specifications
Determine hexadecimal address range from a logic gate diagram
Comparative parameter calculation from percentage differences (NAT)

Paper trends

Shift from straightforward 1-mark address splitting MCQs to multi-variable parameterized equations and MSQ-based address sequence tracing.
2026, 2025, 2024, 2023, 2022, 2021
Increased focus on non-trivial boundary analysis, such as inferring maximum cache size or indexing bounds directly from hex bit patterns.
2026
Consistent dominance of NAT and MSQ formats over standard 4-option MCQs for memory organization questions.
2026, 2025, 2024, 2022, 2021
Shift from linked numerical calculation questions (tag bit widths and directory overhead) to formal algebraic mapping properties and multi-statement conceptual evaluations of multi-level cache write hierarchies.
2021, 2013, 2012
Focus transitioned from direct-mapped total tag directory size calculations to set-associative multi-address bitwise extraction requiring hex-to-binary bit shifting.
2020, 2015, 2011
Memory interfacing appeared in recent years (2023) focusing on non-contiguous or intermediate address line selection (e.g., IA4 and IA3) driving the decoder rather than the traditional MSBs, testing deep binary address decoding rather than rote memorization.
2023
Shift from purely discrete combinational memory expansion design (2013) to numerical performance analysis involving DRAM refresh cycles (2018) and multi-level cache AMAT (2025).
2025, 2018, 2013
Adoption of block diagrams and system architectural figures to test component identification and data flow across registers/memory (2022, 2025).
2025, 2022
Even split between 2-mark conceptual MCQs and precise numerical NAT questions with tight tolerances.
2025, 2022, 2018
Recent examinations focus on exact numerical computation (NAT format) involving execution time, instruction mix tables, and unit conversions (seconds to nanoseconds).
2025
In 2019, questions tested both architectural mapping rules (fully associative cache bit allocations) and hardware interfacing logic (chip-select logic gates) at the 1-mark level.
2019
Questions on CPU performance use numerical percentage variations in execution time and CPI to evaluate exact clock frequencies via NAT format.
2014

Difficulty notes

Easy questions require direct formula application for field splitting (Tag/Index/Offset) or 1-level AMAT. Medium questions involve 2-level caches with separate I/D caches, quadratic AMAT equations, or tracing short 4-word address sequences across iterations. Hard questions involve reverse-engineering bit fields from hex addresses and block constraints (e.g., 2026 S2), virtual indexing aliasing with page coloring (e.g., 2013), or algebraic parameterizations of associativity changes.