Computer Organization and Architecture · Cache Memory and Hierarchy
Official IIT answer key · IIT Bombay · Audited Aug 2026
GATE CSE 2021 Set 2 Q27 · MCQ · 2 marks
Key concept
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Topic notes
Memory hierarchy and cache mapping is one of the highest-yield, most quantitative topics in GATE Computer Science, regularly tested through 2-mark NAT and MSQ questions. GATE focuses heavily on bit-level address field decomposition (Tag, Set/Line Index, Block Offset) across direct, set-associative, and fully-associative caches, as well as multi-level hierarchical Average Memory Access Time (AMAT) calculations. Recent years have increased the emphasis on multi-select questions (MSQs) tracing reference sequences for eviction behavior and comparing write-back versus write-through policies.
Full Cache Memory and Hierarchy guide →Assume a two-level inclusive cache hierarchy, L1 and L2, where L2 is the larger of the two. Consider the following statements. S1 : Read misses in a write through L1 cache do not result in writebacks of dirty lines to the L2. S2 : Write allocate policy must be used in conjunction with write through caches and no-write allocate policy is used with writeback caches. Which of the following statements is correct?
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Independent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.
