Consider a system with 2 KB direct mapped data cache with a block size of 64 bytes. The system has a physical address space of 64 KB and a word length of 16 bits. During the execution of a program, four data words P, Q, R, and S are accessed in that order 10 times (i.e., PQRSPQRS...). Hence, there are 40 accesses to data cache altogether. Assume that the data cache is initially empty and no other data words are accessed by the program. The addresses of the first bytes of P, Q, R, and S are 0xA248, 0xC28A, 0xCA8A, and 0xA262, respectively. For the execution of the above program, which of the following statements is/are TRUE with respect to the data cache?
Select all that applyOne or more correct
Pick every correct option
Solution
Step-by-step verified solution
Official answer: A) Every access to S is a hit.; B) Once P is brought to the cache it is never evicted.; D) Every access to R evicts Q from the cache.
Block Size:64 bytes=26 bytes⟹6 bits for Block Offset
Cache Size:2 KB=2048 bytes
Number of Lines:64 bytes2048 bytes=32=25⟹5 bits for Cache Line Index
Tag Size:16−(5+6)=5 bits
The address fields are:
Address [15:0]=5 bitsTag [15:11]∣5 bitsLine Index [10:6]∣6 bitsBlock Offset [5:0]
Alternatively, Block Number=⌊Address/64⌋ and Line Index=Block Number(mod32).
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### 2. Mapping of P, Q, R, and S
P (0xA248=4154410):
Block Number=⌊41544/64⌋=649
Line Index=649(mod32)=9
Tag=⌊649/32⌋=20
Q (0xC28A=4980210):
Block Number=⌊49802/64⌋=778
Line Index=778(mod32)=10
Tag=⌊778/32⌋=24
R (0xCA8A=5185010):
Block Number=⌊51850/64⌋=810
Line Index=810(mod32)=10
Tag=⌊810/32⌋=25
S (0xA262=4157010):
Block Number=⌊41570/64⌋=649
Line Index=649(mod32)=9
Tag=⌊649/32⌋=20
Observe that:
P and S belong to the same cache block (Block 649) and map to Line 9.
Q and R map to the same Cache Line 10, but belong to different blocks (Block 778 and Block 810).
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### 3. Execution Trace of Access Sequence (P, Q, R, S)×10
Iteration 1:
P: Miss (cold miss) → Block containing both P and S is loaded into Line 9.
Q: Miss (cold miss) → Block containing Q is loaded into Line 10.
R: Miss (conflict miss) → Block containing R replaces Q in Line 10 (evicts Q).
S:Hit→ Block was already brought into Line 9 by P.
Iterations 2 to 10:
P:Hit (Line 9 is undisturbed).
Q: Miss → Evicts R from Line 10.
R: Miss → Evicts Q from Line 10.
S:Hit (Line 9 is undisturbed).
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### 4. Evaluation of Options
(A) True: Every access to S (all 10 accesses, including the first one) is a hit because P is accessed before S in each iteration.
(B) True: Line 9 is never mapped to by Q or R, so once P is brought in during the first access, it is never evicted.
(C) False: At the end of execution, Line 9 contains the block with P and S, and Line 10 contains the block with R. Thus, P, R, and S reside in the cache.
(D) True: Since Q is accessed right before R in every iteration, Q always resides in Line 10 when R is accessed. Therefore, every access to R evicts Q from Line 10.
Determine the cache line index and tag for each address. Note which words belong to the same block/line and trace the reference string P,Q,R,S through the cache.
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GateAI solution cardGATE CSE 2022 · Q54 · MSQ
Consider a system with 2 KB direct mapped data cache with a block size of 64 bytes. The system has a physical address space of 64 KB and a word length of 16 bits. During the execution of a program, four data words P, Q, R, and S are accessed in that order 10 times (i.e., PQRSPQRS...). Hence, there are 40 accesses to data cache altogether. Assume that the data cache is initially empty and no other data words are accessed by the program. The addresses of the first bytes of P, Q, R, and S are 0xA248, 0xC28A, 0xCA8A, and 0xA262, respectively. For the execution of the above program, which of the following statements is/are TRUE with respect to the data cache?