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Cache Memory and Hierarchy

GATE CSE 2022 · Q54

MSQ2 marksMedium

Time

Consider a system with 2 KB direct mapped data cache with a block size of 64 bytes. The system has a physical address space of 64 KB and a word length of 16 bits. During the execution of a program, four data words P, Q, R, and S are accessed in that order 10 times (i.e., PQRSPQRS...). Hence, there are 40 accesses to data cache altogether. Assume that the data cache is initially empty and no other data words are accessed by the program. The addresses of the first bytes of P, Q, R, and S are 0xA248, 0xC28A, 0xCA8A, and 0xA262, respectively. For the execution of the above program, which of the following statements is/are TRUE with respect to the data cache?

Select all that applyOne or more correct

Pick every correct option

Solution

Step-by-step verified solution

Official answer: A) Every access to S is a hit.; B) Once P is brought to the cache it is never evicted.; D) Every access to R evicts Q from the cache.

Cache Memory and Hierarchy

### 1. Cache Parameters and Address Breakdown

  • Physical Address Space:64 KB=216 bytes  ⟹  16-bit address64\text{ KB} = 2^{16}\text{ bytes} \implies 16\text{-bit address}

  • Block Size: 64 bytes=26 bytes  ⟹  6 bits for Block Offset64\text{ bytes} = 2^6\text{ bytes} \implies 6\text{ bits for Block Offset}

  • Cache Size:2 KB=2048 bytes2\text{ KB} = 2048\text{ bytes}

  • Number of Lines: 2048 bytes64 bytes=32=25  ⟹  5 bits for Cache Line Index\frac{2048\text{ bytes}}{64\text{ bytes}} = 32 = 2^5 \implies 5\text{ bits for Cache Line Index}

  • Tag Size:16−(5+6)=5 bits16 - (5 + 6) = 5\text{ bits}

The address fields are:

Address [15:0]=Tag [15:11]⏟5 bits∣Line Index [10:6]⏟5 bits∣Block Offset [5:0]⏟6 bits\text{Address [15:0]} = \underbrace{\text{Tag [15:11]}}_{5\text{ bits}} \mid \underbrace{\text{Line Index [10:6]}}_{5\text{ bits}} \mid \underbrace{\text{Block Offset [5:0]}}_{6\text{ bits}}

Alternatively, Block Number=⌊Address/64⌋\text{Block Number} = \lfloor\text{Address} / 64\rfloor and Line Index=Block Number(mod32)\text{Line Index} = \text{Block Number} \pmod{32}.

---

### 2. Mapping of P, Q, R, and S

  1. P (0xA248=41544100\text{xA248} = 41544_{10}):

    • Block Number=⌊41544/64⌋=649\text{Block Number} = \lfloor 41544 / 64 \rfloor = 649

    • Line Index=649(mod32)=9\text{Line Index} = 649 \pmod{32} = 9

    • Tag=⌊649/32⌋=20\text{Tag} = \lfloor 649 / 32 \rfloor = 20

  2. Q (0xC28A=49802100\text{xC28A} = 49802_{10}):

    • Block Number=⌊49802/64⌋=778\text{Block Number} = \lfloor 49802 / 64 \rfloor = 778

    • Line Index=778(mod32)=10\text{Line Index} = 778 \pmod{32} = 10

    • Tag=⌊778/32⌋=24\text{Tag} = \lfloor 778 / 32 \rfloor = 24

  3. R (0xCA8A=51850100\text{xCA8A} = 51850_{10}):

    • Block Number=⌊51850/64⌋=810\text{Block Number} = \lfloor 51850 / 64 \rfloor = 810

    • Line Index=810(mod32)=10\text{Line Index} = 810 \pmod{32} = 10

    • Tag=⌊810/32⌋=25\text{Tag} = \lfloor 810 / 32 \rfloor = 25

  4. S (0xA262=41570100\text{xA262} = 41570_{10}):

    • Block Number=⌊41570/64⌋=649\text{Block Number} = \lfloor 41570 / 64 \rfloor = 649

    • Line Index=649(mod32)=9\text{Line Index} = 649 \pmod{32} = 9

    • Tag=⌊649/32⌋=20\text{Tag} = \lfloor 649 / 32 \rfloor = 20

Observe that:

  • P and S belong to the same cache block (Block 649) and map to Line 9.

  • Q and R map to the same Cache Line 10, but belong to different blocks (Block 778 and Block 810).

---

### 3. Execution Trace of Access Sequence (P, Q, R, S)×10(\text{P, Q, R, S}) \times 10

  • Iteration 1:

    1. P: Miss (cold miss) →\rightarrow Block containing both P and S is loaded into Line 9.

    2. Q: Miss (cold miss) →\rightarrow Block containing Q is loaded into Line 10.

    3. R: Miss (conflict miss) →\rightarrow Block containing R replaces Q in Line 10 (evicts Q).

    4. S:Hit →\rightarrow Block was already brought into Line 9 by P.

  • Iterations 2 to 10:

    1. P:Hit (Line 9 is undisturbed).

    2. Q: Miss →\rightarrow Evicts R from Line 10.

    3. R: Miss →\rightarrow Evicts Q from Line 10.

    4. S:Hit (Line 9 is undisturbed).

---

### 4. Evaluation of Options

  • (A) True: Every access to S (all 10 accesses, including the first one) is a hit because P is accessed before S in each iteration.

  • (B) True: Line 9 is never mapped to by Q or R, so once P is brought in during the first access, it is never evicted.

  • (C) False: At the end of execution, Line 9 contains the block with P and S, and Line 10 contains the block with R. Thus, P, R, and S reside in the cache.

  • (D) True: Since Q is accessed right before R in every iteration, Q always resides in Line 10 when R is accessed. Therefore, every access to R evicts Q from Line 10.

Hence, the correct options are A, B, and D.

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This Cache Memory and Hierarchy previous year question is Q54 of the GATE CSE 2022 paper. Find more GATE CSE PYQs on Cache Memory and Hierarchy in Computer Organization and Architecture, or browse all GATE CSE PYQs.

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Cache Memory and Hierarchy in GATE CSE

Cache Memory and Hierarchy has 47 GATE CSE PYQs across 23 papers from 2011 to 2026. 3 of them are 2-mark MSQs like this one, and GATE CSE 2022 has 4.

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GateAI solution cardGATE CSE 2022 · Q54 · MSQ

Consider a system with 2 KB direct mapped data cache with a block size of 64 bytes. The system has a physical address space of 64 KB and a word length of 16 bits. During the execution of a program, four data words P, Q, R, and S are accessed in that order 10 times (i.e., PQRSPQRS...). Hence, there are 40 accesses to data cache altogether. Assume that the data cache is initially empty and no other data words are accessed by the program. The addresses of the first bytes of P, Q, R, and S are 0xA248, 0xC28A, 0xCA8A, and 0xA262, respectively. For the execution of the above program, which of the following statements is/are TRUE with respect to the data cache?

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