A partial data path of a processor is given in the figure, where RA, RB, and RZ are 32-bit registers. Which option(s) is/are CORRECT related to arithmetic operations using the data path as shown? A) The data path can implement arithmetic operations involving two registers. B) The data path can implement arithmetic operations involving one register and one immediate value. C) The data path can implement arithmetic operations involving two immediate values. D) The data path can only implement arithmetic operations involving one register and one immediate value.

Official answer: A) The data path can implement arithmetic operations involving two registers.; B) The data path can implement arithmetic operations involving one register and one immediate value.; C) The data path can implement arithmetic operations involving two immediate values.. Explanation: From the given data path: - MuxA has two inputs: the 32-bit register RA and a 32-bit immediate value, controlled by the signal `Select RA/immediate`. - MuxB has two inputs: the 32-bit register RB and a 32-bit immediate value, controlled by the signal `Select RB/immediate`. - Both inputs to the ALU are fed from the outputs of MuxA and MuxB respectively, and the result is stored in the 32-bit register RZ. Since both multiplexers can be controlled independently: 1. Two registers: Selecting RA through MuxA and RB through MuxB feeds both registers into the ALU, allowing arithmetic operations involving two registers. Hence, (A) is correct. 2. One register and one immediate value: Selecting RA and the immediate value (or RB and the immediate value) allows arithmetic operations involving one register and one immediate value. Hence, (B) is correct. 3. Two immediate values: Selecting the immediate value from both MuxA and MuxB allows arithmetic operations involving two immediate values. Hence, (C) is correct. 4. (D) is incorrect because the datapath is not restricted to *only* one register and one immediate value. Thus, the correct options are A, B, and C.

A) The data path can implement arithmetic operations involving two registers.

B) The data path can implement arithmetic operations involving one register and one immediate value.

C) The data path can implement arithmetic operations involving two immediate values.

D) The data path can only implement arithmetic operations involving one register and one immediate value.

Computer Organization and Architecture · ALU Design

Official IIT answer key · IIT Guwahati · Audited Aug 2026

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GATE CSE 2025 Set 1 Q27 · MSQ · 1 mark

A partial data path of a processor is given in the figure, where RA, RB, and RZ are 32-bit registers. Which option(s) is/are CORRECT related to arithmetic operations using the data path as shown?

Select one or more options

Key concept

ALU Design

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How GATE tests ALU Design

Across GATE CS exams (2016–2025), questions on ALU design evaluate three foundational pillars: the timing analysis and gate-level complexity of hardware adders (such as Carry Lookahead Adders), arithmetic algorithms implementation (specifically Booth's algorithm operations), and the integration of the ALU within CPU datapaths (control sequencing and multiplexer-based operand routing). Questions range from 1-mark architectural reasoning items to 2-mark algorithmic/complexity computations.

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Independent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.

Computer Organization and Architecture · ALU Design

Official IIT answer key · IIT Guwahati · Audited Aug 2026

Take topic test

GATE CSE 2025 Set 1 Q27 · MSQ · 1 mark

A partial data path of a processor is given in the figure, where RA, RB, and RZ are 32-bit registers. Which option(s) is/are CORRECT related to arithmetic operations using the data path as shown?

Select one or more options

Key concept

ALU Design

Step-by-step verified solution

Examiner trap & misconception

Topic notes

How GATE tests ALU Design

Full ALU Design guide →

More on ALU Design

All 4 questions on ALU Design →

Independent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.

A partial data path of a processor is given in the figure, where RA, RB, and RZ are 32-bit registers. Which option(s) is/are CORRECT related to arithmetic operations using the data path as shown?

Step-by-step verified solution

Check you can still solve ALU Design under a clock

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A partial data path of a processor is given in the figure, where RA, RB, and RZ are 32-bit registers. Which option(s) is/are CORRECT related to arithmetic operations using the data path as shown?

Step-by-step verified solution

Check you can still solve ALU Design under a clock

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A partial data path of a processor is given in the figure, where RA, RB, and RZ are 32-bit registers. Which option(s) is/are CORRECT related to arithmetic operations using the data path as shown?

Step-by-step verified solution

Check you can still solve ALU Design under a clock

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A partial data path of a processor is given in the figure, where RA, RB, and RZ are 32-bit registers. Which option(s) is/are CORRECT related to arithmetic operations using the data path as shown?

Step-by-step verified solution

Check you can still solve ALU Design under a clock

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