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ALU Design

GATE CSE 2016 Set 1 · Q33

MCQ2 marksMedium

Time

Consider a carry lookahead adder for adding two nn-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is (A) Θ(1)\Theta(1) (B) Θ(log⁡(n))\Theta(\log(n)) (C) Θ(n)\Theta(\sqrt{n}) (D) Θ(n)\Theta(n)

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Solution

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Official answer: B) (log(n))

ALU Design
  1. In an nn-bit Carry Lookahead Adder (CLA):

    • Bit-generate (Gi=AiBiG_i = A_i B_i) and bit-propagate (Pi=Ai⊕BiP_i = A_i \oplus B_i) signals are calculated in parallel in Θ(1)\Theta(1) time using 2-input gates.

    • The carry terms require computing prefix operations (AND/OR trees) over nn variables.

  2. When the fan-in of logic gates is limited to a constant (at most 2), an associative binary operation over nn inputs can be computed using a balanced binary tree of gates.

  3. The depth (height) of such a binary tree with nn inputs is Θ(log⁡2n)\Theta(\log_2 n).

  4. Hence, the total propagation delay to compute all carries and finalize the sum bits using 2-input gates is Θ(log⁡n)\Theta(\log n).

Therefore, the correct option is (B).

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This ALU Design previous year question is Q33 of the GATE CSE 2016 Set 1 paper. Find more GATE CSE PYQs on ALU Design in Computer Organization and Architecture, or browse all GATE CSE PYQs.

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ALU Design in GATE CSE

ALU Design has 4 GATE CSE PYQs across 4 papers from 2016 to 2025. This is the only 2-mark MCQ among them, and it is the only one in GATE CSE 2016 Set 1.

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GateAI solution cardGATE CSE 2016 Set 1 · Q33 · MCQ

Consider a carry lookahead adder for adding two n-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is (A) (1) (B) (log(n)) (C) (√(n)) (D) (n)

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Independent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.