Consider a carry lookahead adder for adding two n-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is (A) (1) (B) (log(n)) (C) (√(n)) (D) (n)
Topic-wise GATE CS PYQs with verified steps
GATE CSE 2016 Set 1 · Q33
Time
Select one answerSingle correct
Solution
Official answer: B) (log(n))
ALU DesignIn an -bit Carry Lookahead Adder (CLA):
Bit-generate () and bit-propagate () signals are calculated in parallel in time using 2-input gates.
The carry terms require computing prefix operations (AND/OR trees) over variables.
When the fan-in of logic gates is limited to a constant (at most 2), an associative binary operation over inputs can be computed using a balanced binary tree of gates.
The depth (height) of such a binary tree with inputs is .
Hence, the total propagation delay to compute all carries and finalize the sum bits using 2-input gates is .
Therefore, the correct option is (B).
Try the question first, then check your work.
Examiner trap
With a constant gate fan-in of 2, computing logical operations across inputs forms a balanced tree structure of logarithmic depth.
This ALU Design previous year question is Q33 of the GATE CSE 2016 Set 1 paper. Find more GATE CSE PYQs on ALU Design in Computer Organization and Architecture, or browse all GATE CSE PYQs.
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ALU Design has 4 GATE CSE PYQs across 4 papers from 2016 to 2025. This is the only 2-mark MCQ among them, and it is the only one in GATE CSE 2016 Set 1.
How GATE tests ALU DesignIndependent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.