Consider a carry lookahead adder for adding two $n$ -bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is (A) $\Theta(1)$ (B) $\Theta(\log(n))$ (C) $\Theta(\sqrt{n})$ (D) $\Theta(n)$

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Key concept

ALU Design

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How GATE tests ALU Design

Across GATE CS exams (2016–2025), questions on ALU design evaluate three foundational pillars: the timing analysis and gate-level complexity of hardware adders (such as Carry Lookahead Adders), arithmetic algorithms implementation (specifically Booth's algorithm operations), and the integration of the ALU within CPU datapaths (control sequencing and multiplexer-based operand routing). Questions range from 1-mark architectural reasoning items to 2-mark algorithmic/complexity computations.

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Computer Organization and Architecture · ALU Design

Official IIT answer key · IISc Bangalore · Audited Aug 2026

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GATE CSE 2016 Set 1 Q33 · MCQ · 2 marks

Consider a carry lookahead adder for adding two $n$ -bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is (A) $\Theta(1)$ (B) $\Theta(\log(n))$ (C) $\Theta(\sqrt{n})$ (D) $\Theta(n)$

Select an option to check

Key concept

ALU Design

Step-by-step verified solution

Examiner trap & misconception

Topic notes

How GATE tests ALU Design

Full ALU Design guide →

More on ALU Design

All 4 questions on ALU Design →

Independent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.

Consider a carry lookahead adder for adding two $n$ -bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is (A) $\Theta(1)$ (B) $\Theta(\log(n))$ (C) $\Theta(\sqrt{n})$ (D) $\Theta(n)$

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Consider a carry lookahead adder for adding two $n$ -bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is (A) $\Theta(1)$ (B) $\Theta(\log(n))$ (C) $\Theta(\sqrt{n})$ (D) $\Theta(n)$

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Check you can still solve ALU Design under a clock

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Consider a carry lookahead adder for adding two nnn-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is (A) Θ(1)\Theta(1)Θ(1) (B) Θ(log⁡(n))\Theta(\log(n))Θ(log(n)) (C) Θ(n)\Theta(\sqrt{n})Θ(n​) (D) Θ(n)\Theta(n)Θ(n)

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Consider a carry lookahead adder for adding two nnn-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is (A) Θ(1)\Theta(1)Θ(1) (B) Θ(log⁡(n))\Theta(\log(n))Θ(log(n)) (C) Θ(n)\Theta(\sqrt{n})Θ(n​) (D) Θ(n)\Theta(n)Θ(n)

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Check you can still solve ALU Design under a clock

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Consider a carry lookahead adder for adding two $n$ -bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is (A) $\Theta(1)$ (B) $\Theta(\log(n))$ (C) $\Theta(\sqrt{n})$ (D) $\Theta(n)$

Consider a carry lookahead adder for adding two $n$ -bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is (A) $\Theta(1)$ (B) $\Theta(\log(n))$ (C) $\Theta(\sqrt{n})$ (D) $\Theta(n)$