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Cache Memory and Hierarchy

GATE CSE 2025 Set 2 · Q55

NAT2 marksMedium

Time

Given a computing system with two levels of cache (L1 and L2) and a main memory. The first level (L1) cache access time is 1 nanosecond (ns) and the “hit rate” for L1 cache is 90% while the processor is accessing the data from L1 cache. Whereas, for the second level (L2) cache, the “hit rate” is 80% and the “miss penalty” for transferring data from L2 cache to L1 cache is 10 ns. The “miss penalty” for the data to be transferred from main memory to L2 cache is 100 ns. Then the average memory access time in this system in nanoseconds is _________ . (rounded off to one decimal place)

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Official answer: 4

Cache Memory and Hierarchy

To calculate the Average Memory Access Time (TavgT_{\text{avg}}) for a hierarchical memory system with two cache levels:

Given data:

  • L1 cache access time, T1=1 nsT_1 = 1\text{ ns}

  • L1 hit rate, H1=90%=0.9H_1 = 90\% = 0.9

  • L1 miss rate, (1−H1)=1−0.9=0.1(1 - H_1) = 1 - 0.9 = 0.1

  • L2 hit rate, H2=80%=0.8H_2 = 80\% = 0.8

  • L2 miss rate, (1−H2)=1−0.8=0.2(1 - H_2) = 1 - 0.8 = 0.2

  • L1 miss penalty (transfer time from L2 to L1), Tpenalty, L2=10 nsT_{\text{penalty, L2}} = 10\text{ ns}

  • L2 miss penalty (transfer time from Main Memory to L2), Tpenalty, MM=100 nsT_{\text{penalty, MM}} = 100\text{ ns}

The average access time is given by:

Tavg=T1+(1−H1)×Miss PenaltyL1T_{\text{avg}} = T_1 + (1 - H_1) \times \text{Miss Penalty}_{L1}

Where the miss penalty at L1 is:

Miss PenaltyL1=Tpenalty, L2+(1−H2)×Tpenalty, MM\text{Miss Penalty}_{L1} = T_{\text{penalty, L2}} + (1 - H_2) \times T_{\text{penalty, MM}}
Miss PenaltyL1=10+0.2×100=10+20=30 ns\text{Miss Penalty}_{L1} = 10 + 0.2 \times 100 = 10 + 20 = 30\text{ ns}

Now substituting back into TavgT_{\text{avg}}:

Tavg=1+0.1×30=1+3=4.0 nsT_{\text{avg}} = 1 + 0.1 \times 30 = 1 + 3 = 4.0\text{ ns}

Thus, the average memory access time is 4.0 ns.

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This Cache Memory and Hierarchy previous year question is Q55 of the GATE CSE 2025 Set 2 paper. Find more GATE CSE PYQs on Cache Memory and Hierarchy in Computer Organization and Architecture, or browse all GATE CSE PYQs.

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Cache Memory and Hierarchy in GATE CSE

Cache Memory and Hierarchy has 47 GATE CSE PYQs across 23 papers from 2011 to 2026. 16 of them are 2-mark NAT questions like this one, and GATE CSE 2025 Set 2 has 3.

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GateAI solution cardGATE CSE 2025 Set 2 · Q55 · NAT

Given a computing system with two levels of cache (L1 and L2) and a main memory. The first level (L1) cache access time is 1 nanosecond (ns) and the “hit rate” for L1 cache is 90% while the processor is accessing the data from L1 cache. Whereas, for the second level (L2) cache, the “hit rate” is 80% and the “miss penalty” for transferring data from L2 cache to L1 cache is 10 ns. The “miss penalty” for the data to be transferred from main memory to L2 cache is 100 ns. Then the average memory access time in this system in nanoseconds is … (rounded off to one decimal place)

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