Computer Organization and Architecture · Cache Memory and Hierarchy
Official IIT answer key · IISc Bangalore · Audited Aug 2026
GATE CSE 2024 Set 1 Q53 · MSQ · 2 marks
Key concept
No account needed
Sit 5 related Cache Memory and HierarchyPYQs as a guest. We'll score the set and show which traps cost marks — sign in only if you want to save the run.
Explore all 109 Computer Organization and Architecture questions
Topic notes
Memory hierarchy and cache mapping is one of the highest-yield, most quantitative topics in GATE Computer Science, regularly tested through 2-mark NAT and MSQ questions. GATE focuses heavily on bit-level address field decomposition (Tag, Set/Line Index, Block Offset) across direct, set-associative, and fully-associative caches, as well as multi-level hierarchical Average Memory Access Time (AMAT) calculations. Recent years have increased the emphasis on multi-select questions (MSQs) tracing reference sequences for eviction behavior and comparing write-back versus write-through policies.
Full Cache Memory and Hierarchy guide →Consider two set-associative cache memory architectures: WBC, which uses the write back policy, and WTC, which uses the write through policy. Both of them use the LRU ( Least Recently Used) block replacement policy. The cache memory is connected to the main memory. Which of the following statements is/are TRUE?
Topic-wise GATE CS PYQs with verified steps
Independent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.
