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Cache Memory and Hierarchy

GATE CSE 2025 Set 1 · Q53

NAT2 marksMedium

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A computer has a memory hierarchy consisting of two-level cache (L1 and L2) and a main memory. If the processor needs to access data from memory, it first looks into L1 cache. If the data is not found in L1 cache, it goes to L2 cache. If it fails to get the data from L2 cache, it goes to main memory, where the data is definitely available. Hit rates and access times of various memory units are shown in the figure. The average memory access time in nanoseconds (nsns) is ________. (rounded off to two decimal places)

GATE CSE 2025 Set 1 Q53 diagram

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Official answer: 11.85 (±0.02) (±0.02)

Cache Memory and Hierarchy

To find the Average Memory Access Time (AMATAMAT):

Given data from the hierarchy:

  • L1 Cache:

    • Hit rate (H1H_1) = 95%=0.9595\% = 0.95

    • Miss rate (M1M_1) = 1−0.95=0.051 - 0.95 = 0.05

    • Access time (T1T_1) = 10 ns10\text{ ns}

  • L2 Cache:

    • Hit rate (H2H_2) = 85%=0.8585\% = 0.85

    • Miss rate (M2M_2) = 1−0.85=0.151 - 0.85 = 0.15

    • Access time (including L1 cache miss penalty) (T2T_2) = 20 ns20\text{ ns}

  • Main Memory:

    • Access time (including L1 and L2 cache miss penalty) (TmT_m) = 200 ns200\text{ ns}

Since the access times for L2 and Main Memory already include the miss penalties of previous levels (hierarchical access):

AMAT=H1×T1+M1×(H2×T2+M2×Tm)=0.95×10+0.05×(0.85×20+0.15×200)=9.5+0.05×(17+30)=9.5+0.05×47=9.5+2.35=11.85 ns\begin{aligned} AMAT &= H_1 \times T_1 + M_1 \times \left( H_2 \times T_2 + M_2 \times T_m \right) \\ &= 0.95 \times 10 + 0.05 \times \left( 0.85 \times 20 + 0.15 \times 200 \right) \\ &= 9.5 + 0.05 \times (17 + 30) \\ &= 9.5 + 0.05 \times 47 \\ &= 9.5 + 2.35 \\ &= 11.85\text{ ns} \end{aligned}

Hence, the average memory access time is 11.85 ns\text{ns} [range: 11.83 to 11.87].

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This Cache Memory and Hierarchy previous year question is Q53 of the GATE CSE 2025 Set 1 paper. Find more GATE CSE PYQs on Cache Memory and Hierarchy in Computer Organization and Architecture, or browse all GATE CSE PYQs.

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Cache Memory and Hierarchy in GATE CSE

Cache Memory and Hierarchy has 47 GATE CSE PYQs across 23 papers from 2011 to 2026. 16 of them are 2-mark NAT questions like this one, and GATE CSE 2025 Set 1 has 2.

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A computer has a memory hierarchy consisting of two-level cache (L1 and L2) and a main memory. If the processor needs to access data from memory, it first looks into L1 cache. If the data is not found in L1 cache, it goes to L2 cache. If it fails to get the data from L2 cache, it goes to main memory, where the data is definitely available. Hit rates and access times of various memory units are shown in the figure. The average memory access time in nanoseconds (ns) is … (rounded off to two decimal places)

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