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I/O Interface, Interrupts and DMA

GATE CSE 2021 Set 2 · Q20

NAT1 markEasy

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Consider a computer system with DMA support. The DMA module is transferring one 8-bit character in one CPU cycle from a device to memory through cycle stealing at regular intervals. Consider a 2 MHz processor. If 0.5% processor cycles are used for DMA, the data transfer rate of the device is ________ bits per second.

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Official answer: 80000

I/O Interface, Interrupts and DMA

Given:

  • Processor frequency = 2 MHz=2×106 cycles/second2\text{ MHz} = 2 \times 10^6\text{ cycles/second}

  • Percentage of cycles stolen by DMA = 0.5%=0.0050.5\% = 0.005

  • Data transferred per cycle = 1 character=8 bits1\text{ character} = 8\text{ bits}

Number of DMA cycles per second:

DMA cycles=0.005×(2×106)=10,000 cycles/second\text{DMA cycles} = 0.005 \times (2 \times 10^6) = 10,000\text{ cycles/second}

Data transfer rate of the device:

Transfer Rate=10,000×8 bits/second=80,000 bits per second\text{Transfer Rate} = 10,000 \times 8\text{ bits/second} = 80,000\text{ bits per second}

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This I/O Interface, Interrupts and DMA previous year question is Q20 of the GATE CSE 2021 Set 2 paper. Find more GATE CSE PYQs on I/O Interface, Interrupts and DMA in Computer Organization and Architecture, or browse all GATE CSE PYQs.

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I/O Interface, Interrupts and DMA in GATE CSE

I/O Interface, Interrupts and DMA has 13 GATE CSE PYQs across 12 papers from 2011 to 2026. 2 of them are 1-mark NAT questions like this one, and it is the only one in GATE CSE 2021 Set 2.

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GateAI solution cardGATE CSE 2021 Set 2 · Q20 · NAT

Consider a computer system with DMA support. The DMA module is transferring one 8-bit character in one CPU cycle from a device to memory through cycle stealing at regular intervals. Consider a 2 MHz processor. If 0.5% processor cycles are used for DMA, the data transfer rate of the device is … bits per second.

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