Computer Organization and Architecture · I/O Interface, Interrupts and DMA
Official IIT answer key · IIT Bombay · Audited Aug 2026
GATE CSE 2021 Set 2 Q20 · NAT · 1 mark
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Topic notes
GATE tests I/O interface (Interrupt and DMA) across two main facets: conceptual understanding of I/O transfer mechanisms (Programmed I/O, Interrupt-driven I/O, and DMA modes) alongside quantitative calculations on DMA bandwidth, cycle stealing, and register limits. Conceptual questions regularly assess interrupt lifecycle events, priority resolution (Daisy chaining vs Polling), and vectored vs non-vectored interrupt handling. Numerical questions focus on DMA throughput given processor clock frequency and stolen cycle percentages, as well as transfer chunking governed by DMA data counter bit-widths.
Full I/O Interface, Interrupts and DMA guide →Consider a computer system with DMA support. The DMA module is transferring one 8-bit character in one CPU cycle from a device to memory through cycle stealing at regular intervals. Consider a 2 MHz processor. If 0.5% processor cycles are used for DMA, the data transfer rate of the device is … bits per second.
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