Consider the following statements. I. Daisy chaining is used to assign priorities in attending interrupts. II. When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt. III. In polling, the CPU periodically checks the status bits to know if any device needs its attention. IV. During DMA, both the CPU and DMA controller can be bus masters at the same time. Which of the above statements is/are TRUE?

Evaluating each statement:

• Statement I is TRUE: Daisy chaining is a hardware priority mechanism in which the interrupt grant signal propagates serially through devices in order of their priority.

• Statement II is FALSE: In vectored interrupts, the interrupting device itself supplies the vector (address of the service routine) directly onto the data bus, eliminating the need for software polling by the CPU.

• Statement III is TRUE: In polling (programmed I/O), the CPU periodically reads the status register/bits of connected I/O devices in a loop to check if any device requires service.

• Statement IV is FALSE: At any given time, only one device can control the system bus to avoid bus contention; the CPU and DMA controller cannot both be bus masters simultaneously.

Therefore, statements I and III only are TRUE, which corresponds to option (C).