Computer Organization and Architecture · I/O Interface, Interrupts and DMA
Official IIT answer key · IISc Bangalore · Audited Aug 2026
GATE CSE 2024 Set 2 Q11 · MCQ · 1 mark
Key concept
No account needed
Sit 5 related I/O Interface, Interrupts and DMAPYQs as a guest. We'll score the set and show which traps cost marks — sign in only if you want to save the run.
Explore all 109 Computer Organization and Architecture questions
Topic notes
GATE tests I/O interface (Interrupt and DMA) across two main facets: conceptual understanding of I/O transfer mechanisms (Programmed I/O, Interrupt-driven I/O, and DMA modes) alongside quantitative calculations on DMA bandwidth, cycle stealing, and register limits. Conceptual questions regularly assess interrupt lifecycle events, priority resolution (Daisy chaining vs Polling), and vectored vs non-vectored interrupt handling. Numerical questions focus on DMA throughput given processor clock frequency and stolen cycle percentages, as well as transfer chunking governed by DMA data counter bit-widths.
Full I/O Interface, Interrupts and DMA guide →Consider a computer with a 4 MHz processor. Its DMA controller can transfer 8 bytes in 1 cycle from a device to main memory through cycle stealing at regular intervals. Which one of the following is the data transfer rate ( in bits per second) of the DMA controller if 1% of the processor cycles are used for DMA?
Topic-wise GATE CS PYQs with verified steps
Independent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.
