Loading previous year questions
Computer Organization and Architecture · Instruction Set and Addressing Modes
Official IIT answer key · IIT Kanpur · Audited Aug 2026
GATE CSE 2015 Set 1 Q8 · MCQ · 1 mark
Key concept
No account needed
Sit 5 related Instruction Set and Addressing ModesPYQs as a guest. We'll score the set and show which traps cost marks — sign in only if you want to save the run.
Explore all 109 Computer Organization and Architecture questions
Topic notes
Instruction set and addressing modes in GATE CS is consistently tested through instruction word encoding, expanding opcode schemes, addressing mode semantics, and ISA architectural principles. Problems evaluate a candidate's ability to calculate bit allocations for opcodes, register specifiers, and immediates, as well as mapping high-level constructs (structs, arrays, pointers) to assembly addressing modes. The topic features a healthy mix of conceptual 1-mark MCQs/MSQs and rigorous 2-mark NATs involving bit calculations and assembly program traces.
Full Instruction Set and Addressing Modes guide →For computers based on three-address instruction formats, each address field can be used to specify which of the following: (S1) A memory operand (S2) A processor register (S3) An implied accumulator register
Topic-wise GATE CS PYQs with verified steps
Independent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.