Key characteristics of a Reduced Instruction Set Computer (RISC) architecture include:
Load/Store architecture: Arithmetic and logical operations are performed only on data stored in registers (register-to-register operations). Only specific load and store instructions access memory (Characteristic I).
Fixed-length instructions: Instructions typically have a standard fixed size (e.g., 32 bits), which simplifies instruction decoding and pipelining (Characteristic II).
Hardwired control unit: RISC uses simple instructions executed in a single cycle, which are most efficiently implemented using a fast hardwired control unit rather than microprogrammed control (Characteristic III).
Since all three characteristics (I, II, and III) are core design principles of RISC processors, D is the correct option.