A computer has a 256 KByte, 4-way set associative, write back data cache with block size of 32 Bytes. The processor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit. The size of the cache tag directory is

From the cache specifications:

• Total number of cache lines $= \frac{256\text{ KB}}{32\text{ B}} = 8192 = 2^{13}$ lines.

• Tag bits per entry $= 16\text{ bits}$.

Each entry in the cache tag directory contains:

• Tag: $16\text{ bits}$

• Valid bits: $2\text{ bits}$

• Modified bit: $1\text{ bit}$

• Replacement bit: $1\text{ bit}$

There is one directory entry per cache block (line):

Thus, the correct answer is 160 Kbits (Option A).