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Cache Memory and Hierarchy

GATE CSE 2014 Set 2 · Q43

MCQ2 marksMedium

Time

In designing a computer's cache system, the cache block (or cache line) size is an important parameter. Which one of the following statements is correct in this context?

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Solution

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Official answer: D) A smaller block size incurs a lower cache miss penalty

Cache Memory and Hierarchy

Let us evaluate the effects of changing the cache block size:

  • Miss Penalty: Miss penalty is the time taken to bring a block from main memory to the cache on a cache miss. Since smaller blocks contain fewer bytes, transferring a smaller block takes less time (fewer memory transfer cycles), which means a smaller block size incurs a lower cache miss penalty. Hence, (D) is correct.

  • Spatial Locality: Larger block sizes generally exploit spatial locality better (up to a certain point) because fetching a larger contiguous chunk brings nearby words that are likely to be accessed soon. A smaller block size reduces spatial locality advantages, so (A) is incorrect.

  • Tag Overhead: The number of blocks is given by Cache SizeBlock Size\frac{\text{Cache Size}}{\text{Block Size}}. Smaller block sizes increase the number of blocks/lines in the cache, requiring more tag entries and larger tag widths (since fewer offset bits means more tag bits for a fixed number of sets or lines), thus *increasing* tag overhead. Therefore, (B) is incorrect.

  • Hit Time: Larger tag sizes require wider comparators, which can slightly increase or not decrease hit time. More importantly, (D) directly states the fundamental trade-off: smaller block size →\rightarrow lower miss penalty.

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This Cache Memory and Hierarchy previous year question is Q43 of the GATE CSE 2014 Set 2 paper. Find more GATE CSE PYQs on Cache Memory and Hierarchy in Computer Organization and Architecture, or browse all GATE CSE PYQs.

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Cache Memory and Hierarchy in GATE CSE

Cache Memory and Hierarchy has 47 GATE CSE PYQs across 23 papers from 2011 to 2026. 16 of them are 2-mark MCQs like this one, and GATE CSE 2014 Set 2 has 4.

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GateAI solution cardGATE CSE 2014 Set 2 · Q43 · MCQ

In designing a computer's cache system, the cache block (or cache line) size is an important parameter. Which one of the following statements is correct in this context?

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Independent practice explanation verified by the GateAI team. GATE is conducted by the IITs; question text follows the official paper.